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bit write update

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This commit is contained in:
David Harris 2022-03-09 19:09:20 +00:00
parent 27f09ffb33
commit bc2b757952
1 changed files with 1 additions and 10 deletions
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pipelined/src/ifu/SRAM2P1R1W.sv
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@ -101,17 +101,8 @@ module SRAM2P1R1W
// write port // write port
assign bwe = {WIDTH{WEN1Q}} & BitWEN1; assign bwe = {WIDTH{WEN1Q}} & BitWEN1;
always_ff @(posedge clk) begin always_ff @(posedge clk)
mem[WA1Q] <= WD1Q & bwe | mem[WA1Q] & ~bwe; mem[WA1Q] <= WD1Q & bwe | mem[WA1Q] & ~bwe;
/*
genvar index;
for (index = 0; index < WIDTH; index = index + 1) begin:bitwrite
always_ff @(posedge clk) begin
if (WEN1Q & BitWEN1[index]) begin
mem[WA1Q][index] <= WD1Q[index];
end
end*/
end
endmodule endmodule