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Merge pull request #533 from ross144/main

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Finally fixed the store delay hazard bug.
This commit is contained in:
David Harris 2023-12-15 19:13:53 -08:00 committed by GitHub
commit bbdcfe24ca
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GPG Key ID: 4AEE18F83AFDEB23
6 changed files with 161 additions and 204 deletions
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3
fpga/constraints/marked_debug.txt
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@ -7,6 +7,3 @@ lsu/lsu.sv: logic PAdrM
lsu/lsu.sv: logic ReadDataM lsu/lsu.sv: logic ReadDataM
lsu/lsu.sv: logic WriteDataM lsu/lsu.sv: logic WriteDataM
lsu/lsu.sv: logic MemRWM lsu/lsu.sv: logic MemRWM
mmu/hptw.sv: logic SATP_REGW
privileged/csr.sv: logic MENVCFG_REGW
privileged/csr.sv: logic SENVCFG_REGW

33
fpga/constraints/small-debug.xdc
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File diff suppressed because one or more lines are too long

16
fpga/generator/Makefile
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@ -6,17 +6,17 @@ dst := IP
#export board := vcu118 #export board := vcu118
# vcu108 # vcu108
export XILINX_PART := xcvu095-ffva2104-2-e #export XILINX_PART := xcvu095-ffva2104-2-e
export XILINX_BOARD := xilinx.com:vcu108:part0:1.2 #export XILINX_BOARD := xilinx.com:vcu108:part0:1.2
export board := vcu108 #export board := vcu108
# Arty A7 # Arty A7
# export XILINX_PART := xc7a100tcsg324-1 export XILINX_PART := xc7a100tcsg324-1
# export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1 export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
# export board := ArtyA7 export board := ArtyA7
# for Arty A7 and S7 boards # for Arty A7 and S7 boards
all: FPGA_VCU all: FPGA_Arty
# VCU 108 and VCU 118 boards # VCU 108 and VCU 118 boards
#all: FPGA_VCU #all: FPGA_VCU
@ -54,7 +54,7 @@ PreProcessFiles:
cp ../../config/rv64gc/config.vh ../src/CopiedFiles_do_not_add_to_repo/config/ cp ../../config/rv64gc/config.vh ../src/CopiedFiles_do_not_add_to_repo/config/
./insert_debug_comment.sh ./insert_debug_comment.sh
# modify config *** RT: eventually setup for variably defined sized memory # modify config *** RT: eventually setup for variably defined sized memory
sed -i "s/ZICCLSM_SUPPORTED.*/ZICCLSM_SUPPORTED = 0;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh sed -i "s/ZICCLSM_SUPPORTED.*/ZICCLSM_SUPPORTED = 1;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/RESET_VECTOR.*/RESET_VECTOR = 64'h0000000000001000;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh sed -i "s/RESET_VECTOR.*/RESET_VECTOR = 64'h0000000000001000;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/BOOTROM_PRELOAD.*/BOOTROM_PRELOAD = 1'b1;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh sed -i "s/BOOTROM_PRELOAD.*/BOOTROM_PRELOAD = 1'b1;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/UNCORE_RAM_BASE.*/UNCORE_RAM_BASE = 64'h00002000;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh sed -i "s/UNCORE_RAM_BASE.*/UNCORE_RAM_BASE = 64'h00002000;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh

4
fpga/generator/wally.tcl
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@ -14,10 +14,10 @@ if {$boardName!="ArtyA7"} {
# read package first # read package first
read_verilog -sv ../src/CopiedFiles_do_not_add_to_repo/cvw.sv read_verilog -sv ../src/CopiedFiles_do_not_add_to_repo/cvw.sv
read_verilog -sv ../src/wallypipelinedsocwrapper.sv #read_verilog -sv ../src/wallypipelinedsocwrapper.sv
# then read top level # then read top level
if {$board=="ArtyA7"} { if {$board=="ArtyA7"} {
read_verilog {../src/fpgaTopArtyA7.v} read_verilog {../src/fpgaTopArtyA7.sv}
} else { } else {
read_verilog {../src/fpgaTop.v} read_verilog {../src/fpgaTop.v}
} }

307
fpga/src/fpgaTopArtyA7.v → fpga/src/fpgaTopArtyA7.sv
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@ -24,6 +24,10 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/////////////////////////////////////////// ///////////////////////////////////////////
`include "config.vh"
import cvw::*;
module fpgaTop module fpgaTop
(input default_100mhz_clk, (input default_100mhz_clk,
(* mark_debug = "true" *) input resetn, (* mark_debug = "true" *) input resetn,
@ -58,12 +62,12 @@ module fpgaTop
); );
wire CPUCLK; wire CPUCLK;
(* mark_debug = "true" *) wire c0_ddr4_ui_clk_sync_rst; wire c0_ddr4_ui_clk_sync_rst;
(* mark_debug = "true" *) wire bus_struct_reset; wire bus_struct_reset;
(* mark_debug = "true" *) wire peripheral_reset; wire peripheral_reset;
(* mark_debug = "true" *) wire interconnect_aresetn; wire interconnect_aresetn;
(* mark_debug = "true" *) wire peripheral_aresetn; wire peripheral_aresetn;
(* mark_debug = "true" *) wire mb_reset; wire mb_reset;
wire HCLKOpen; wire HCLKOpen;
wire HRESETnOpen; wire HRESETnOpen;
@ -171,48 +175,48 @@ module fpgaTop
// Crossbar to Bus ------------------------------------------------ // Crossbar to Bus ------------------------------------------------
(* mark_debug = "true" *)wire s00_axi_aclk; wire s00_axi_aclk;
(* mark_debug = "true" *)wire s00_axi_aresetn; wire s00_axi_aresetn;
(* mark_debug = "true" *)wire [3:0] s00_axi_awid; wire [3:0] s00_axi_awid;
(* mark_debug = "true" *)wire [31:0]s00_axi_awaddr; wire [31:0]s00_axi_awaddr;
(* mark_debug = "true" *)wire [7:0]s00_axi_awlen; wire [7:0]s00_axi_awlen;
(* mark_debug = "true" *)wire [2:0]s00_axi_awsize; wire [2:0]s00_axi_awsize;
(* mark_debug = "true" *)wire [1:0]s00_axi_awburst; wire [1:0]s00_axi_awburst;
(* mark_debug = "true" *)wire [0:0]s00_axi_awlock; wire [0:0]s00_axi_awlock;
(* mark_debug = "true" *)wire [3:0]s00_axi_awcache; wire [3:0]s00_axi_awcache;
(* mark_debug = "true" *)wire [2:0]s00_axi_awprot; wire [2:0]s00_axi_awprot;
(* mark_debug = "true" *)wire [3:0]s00_axi_awregion; wire [3:0]s00_axi_awregion;
(* mark_debug = "true" *)wire [3:0]s00_axi_awqos; wire [3:0]s00_axi_awqos;
(* mark_debug = "true" *) wire s00_axi_awvalid; wire s00_axi_awvalid;
(* mark_debug = "true" *) wire s00_axi_awready; wire s00_axi_awready;
(* mark_debug = "true" *)wire [63:0]s00_axi_wdata; wire [63:0]s00_axi_wdata;
(* mark_debug = "true" *)wire [7:0]s00_axi_wstrb; wire [7:0]s00_axi_wstrb;
(* mark_debug = "true" *)wire s00_axi_wlast; wire s00_axi_wlast;
(* mark_debug = "true" *)wire s00_axi_wvalid; wire s00_axi_wvalid;
(* mark_debug = "true" *)wire s00_axi_wready; wire s00_axi_wready;
(* mark_debug = "true" *)wire [1:0]s00_axi_bresp; wire [1:0]s00_axi_bresp;
(* mark_debug = "true" *)wire s00_axi_bvalid; wire s00_axi_bvalid;
(* mark_debug = "true" *)wire s00_axi_bready; wire s00_axi_bready;
wire [3:0] s00_axi_arid; wire [3:0] s00_axi_arid;
(* mark_debug = "true" *)wire [31:0]s00_axi_araddr; wire [31:0]s00_axi_araddr;
(* mark_debug = "true" *)wire [7:0]s00_axi_arlen; wire [7:0]s00_axi_arlen;
(* mark_debug = "true" *)wire [2:0]s00_axi_arsize; wire [2:0]s00_axi_arsize;
(* mark_debug = "true" *)wire [1:0]s00_axi_arburst; wire [1:0]s00_axi_arburst;
(* mark_debug = "true" *)wire [0:0]s00_axi_arlock; wire [0:0]s00_axi_arlock;
(* mark_debug = "true" *)wire [3:0]s00_axi_arcache; wire [3:0]s00_axi_arcache;
(* mark_debug = "true" *)wire [2:0]s00_axi_arprot; wire [2:0]s00_axi_arprot;
(* mark_debug = "true" *)wire [3:0]s00_axi_arregion; wire [3:0]s00_axi_arregion;
(* mark_debug = "true" *)wire [3:0]s00_axi_arqos; wire [3:0]s00_axi_arqos;
(* mark_debug = "true" *)wire s00_axi_arvalid; wire s00_axi_arvalid;
(* mark_debug = "true" *)wire s00_axi_arready; wire s00_axi_arready;
(* mark_debug = "true" *)wire [63:0]s00_axi_rdata; wire [63:0]s00_axi_rdata;
(* mark_debug = "true" *)wire [1:0]s00_axi_rresp; wire [1:0]s00_axi_rresp;
(* mark_debug = "true" *)wire s00_axi_rlast; wire s00_axi_rlast;
(* mark_debug = "true" *)wire s00_axi_rvalid; wire s00_axi_rvalid;
(* mark_debug = "true" *)wire s00_axi_rready; wire s00_axi_rready;
(* mark_debug = "true" *)wire [3:0] s00_axi_bid; wire [3:0] s00_axi_bid;
(* mark_debug = "true" *)wire [3:0] s00_axi_rid; wire [3:0] s00_axi_rid;
// 64to32 dwidth converter input interface------------------------- // 64to32 dwidth converter input interface-------------------------
wire s01_axi_aclk; wire s01_axi_aclk;
@ -227,8 +231,8 @@ module fpgaTop
wire [2:0]s01_axi_awprot; wire [2:0]s01_axi_awprot;
wire [3:0]s01_axi_awregion; wire [3:0]s01_axi_awregion;
wire [3:0]s01_axi_awqos; // qos signals need to be 0 for SDC wire [3:0]s01_axi_awqos; // qos signals need to be 0 for SDC
(* mark_debug = "true" *) wire s01_axi_awvalid; wire s01_axi_awvalid;
(* mark_debug = "true" *) wire s01_axi_awready; wire s01_axi_awready;
wire [63:0]s01_axi_wdata; wire [63:0]s01_axi_wdata;
wire [7:0]s01_axi_wstrb; wire [7:0]s01_axi_wstrb;
wire s01_axi_wlast; wire s01_axi_wlast;
@ -265,8 +269,8 @@ module fpgaTop
wire [2:0]axi4in_axi_awprot; wire [2:0]axi4in_axi_awprot;
wire [3:0]axi4in_axi_awregion; wire [3:0]axi4in_axi_awregion;
wire [3:0]axi4in_axi_awqos; wire [3:0]axi4in_axi_awqos;
(* mark_debug = "true" *) wire axi4in_axi_awvalid; wire axi4in_axi_awvalid;
(* mark_debug = "true" *) wire axi4in_axi_awready; wire axi4in_axi_awready;
wire [31:0]axi4in_axi_wdata; wire [31:0]axi4in_axi_wdata;
wire [3:0]axi4in_axi_wstrb; wire [3:0]axi4in_axi_wstrb;
wire axi4in_axi_wlast; wire axi4in_axi_wlast;
@ -293,30 +297,30 @@ module fpgaTop
wire axi4in_axi_rready; wire axi4in_axi_rready;
// AXI4 to AXI4-Lite Protocol converter output // AXI4 to AXI4-Lite Protocol converter output
(* mark_debug = "true" *) wire [31:0]SDCin_axi_awaddr; wire [31:0]SDCin_axi_awaddr;
(* mark_debug = "true" *) wire [2:0]SDCin_axi_awprot; wire [2:0]SDCin_axi_awprot;
(* mark_debug = "true" *) wire SDCin_axi_awvalid; wire SDCin_axi_awvalid;
(* mark_debug = "true" *) wire SDCin_axi_awready; wire SDCin_axi_awready;
(* mark_debug = "true" *) wire [31:0]SDCin_axi_wdata; wire [31:0]SDCin_axi_wdata;
(* mark_debug = "true" *) wire [3:0]SDCin_axi_wstrb; wire [3:0]SDCin_axi_wstrb;
(* mark_debug = "true" *) wire SDCin_axi_wvalid; wire SDCin_axi_wvalid;
(* mark_debug = "true" *) wire SDCin_axi_wready; wire SDCin_axi_wready;
(* mark_debug = "true" *) wire [1:0]SDCin_axi_bresp; wire [1:0]SDCin_axi_bresp;
(* mark_debug = "true" *) wire SDCin_axi_bvalid; wire SDCin_axi_bvalid;
(* mark_debug = "true" *) wire SDCin_axi_bready; wire SDCin_axi_bready;
(* mark_debug = "true" *) wire [31:0]SDCin_axi_araddr; wire [31:0]SDCin_axi_araddr;
(* mark_debug = "true" *) wire [2:0]SDCin_axi_arprot; wire [2:0]SDCin_axi_arprot;
(* mark_debug = "true" *) wire SDCin_axi_arvalid; wire SDCin_axi_arvalid;
(* mark_debug = "true" *) wire SDCin_axi_arready; wire SDCin_axi_arready;
(* mark_debug = "true" *) wire [31:0]SDCin_axi_rdata; wire [31:0]SDCin_axi_rdata;
(* mark_debug = "true" *) wire [1:0]SDCin_axi_rresp; wire [1:0]SDCin_axi_rresp;
(* mark_debug = "true" *) wire SDCin_axi_rvalid; wire SDCin_axi_rvalid;
(* mark_debug = "true" *) wire SDCin_axi_rready; wire SDCin_axi_rready;
// ---------------------------------------------------------------- // ----------------------------------------------------------------
// 32to64 dwidth converter input interface ----------------------- // 32to64 dwidth converter input interface -----------------------
(* mark_debug = "true" *) wire [31:0]SDCout_axi_awaddr; wire [31:0]SDCout_axi_awaddr;
(* mark_debug = "true" *) wire [7:0]SDCout_axi_awlen; wire [7:0]SDCout_axi_awlen;
wire [2:0]SDCout_axi_awsize; wire [2:0]SDCout_axi_awsize;
wire [1:0]SDCout_axi_awburst; wire [1:0]SDCout_axi_awburst;
wire [0:0]SDCout_axi_awlock; wire [0:0]SDCout_axi_awlock;
@ -324,16 +328,16 @@ module fpgaTop
wire [2:0]SDCout_axi_awprot; wire [2:0]SDCout_axi_awprot;
wire [3:0]SDCout_axi_awregion; wire [3:0]SDCout_axi_awregion;
wire [3:0]SDCout_axi_awqos; wire [3:0]SDCout_axi_awqos;
(* mark_debug = "true" *) wire SDCout_axi_awvalid; wire SDCout_axi_awvalid;
(* mark_debug = "true" *) wire SDCout_axi_awready; wire SDCout_axi_awready;
(* mark_debug = "true" *) wire [31:0]SDCout_axi_wdata; wire [31:0]SDCout_axi_wdata;
wire [3:0]SDCout_axi_wstrb; wire [3:0]SDCout_axi_wstrb;
(* mark_debug = "true" *) wire SDCout_axi_wlast; wire SDCout_axi_wlast;
(* mark_debug = "true" *) wire SDCout_axi_wvalid; wire SDCout_axi_wvalid;
(* mark_debug = "true" *)wire SDCout_axi_wready; wire SDCout_axi_wready;
(* mark_debug = "true" *) wire [1:0]SDCout_axi_bresp; wire [1:0]SDCout_axi_bresp;
(* mark_debug = "true" *) wire SDCout_axi_bvalid; wire SDCout_axi_bvalid;
(* mark_debug = "true" *) wire SDCout_axi_bready; wire SDCout_axi_bready;
wire [31:0]SDCout_axi_araddr; wire [31:0]SDCout_axi_araddr;
wire [7:0]SDCout_axi_arlen; wire [7:0]SDCout_axi_arlen;
wire [2:0]SDCout_axi_arsize; wire [2:0]SDCout_axi_arsize;
@ -352,45 +356,45 @@ module fpgaTop
wire SDCout_axi_rready; wire SDCout_axi_rready;
// Output Interface // Output Interface
(* mark_debug = "true" *) wire [3:0]m01_axi_awid; wire [3:0]m01_axi_awid;
(* mark_debug = "true" *) wire [31:0]m01_axi_awaddr; wire [31:0]m01_axi_awaddr;
(* mark_debug = "true" *) wire [7:0]m01_axi_awlen; wire [7:0]m01_axi_awlen;
(* mark_debug = "true" *) wire [2:0]m01_axi_awsize; wire [2:0]m01_axi_awsize;
(* mark_debug = "true" *) wire [1:0]m01_axi_awburst; wire [1:0]m01_axi_awburst;
(* mark_debug = "true" *) wire [0:0]m01_axi_awlock; wire [0:0]m01_axi_awlock;
(* mark_debug = "true" *) wire [3:0]m01_axi_awcache; wire [3:0]m01_axi_awcache;
(* mark_debug = "true" *) wire [2:0]m01_axi_awprot; wire [2:0]m01_axi_awprot;
(* mark_debug = "true" *) wire [3:0]m01_axi_awregion; wire [3:0]m01_axi_awregion;
(* mark_debug = "true" *) wire [3:0]m01_axi_awqos; wire [3:0]m01_axi_awqos;
(* mark_debug = "true" *) wire m01_axi_awvalid; wire m01_axi_awvalid;
(* mark_debug = "true" *) wire m01_axi_awready; wire m01_axi_awready;
(* mark_debug = "true" *) wire [63:0]m01_axi_wdata; wire [63:0]m01_axi_wdata;
(* mark_debug = "true" *) wire [7:0]m01_axi_wstrb; wire [7:0]m01_axi_wstrb;
(* mark_debug = "true" *) wire m01_axi_wlast; wire m01_axi_wlast;
(* mark_debug = "true" *) wire m01_axi_wvalid; wire m01_axi_wvalid;
(* mark_debug = "true" *) wire m01_axi_wready; wire m01_axi_wready;
(* mark_debug = "true" *) wire [3:0] m01_axi_bid; wire [3:0] m01_axi_bid;
(* mark_debug = "true" *) wire [1:0]m01_axi_bresp; wire [1:0]m01_axi_bresp;
(* mark_debug = "true" *) wire m01_axi_bvalid; wire m01_axi_bvalid;
(* mark_debug = "true" *) wire m01_axi_bready; wire m01_axi_bready;
(* mark_debug = "true" *) wire [3:0] m01_axi_arid; wire [3:0] m01_axi_arid;
(* mark_debug = "true" *) wire [31:0]m01_axi_araddr; wire [31:0]m01_axi_araddr;
(* mark_debug = "true" *) wire [7:0]m01_axi_arlen; wire [7:0]m01_axi_arlen;
(* mark_debug = "true" *) wire [2:0]m01_axi_arsize; wire [2:0]m01_axi_arsize;
(* mark_debug = "true" *) wire [1:0]m01_axi_arburst; wire [1:0]m01_axi_arburst;
(* mark_debug = "true" *) wire [0:0]m01_axi_arlock; wire [0:0]m01_axi_arlock;
(* mark_debug = "true" *) wire [3:0]m01_axi_arcache; wire [3:0]m01_axi_arcache;
(* mark_debug = "true" *) wire [2:0]m01_axi_arprot; wire [2:0]m01_axi_arprot;
(* mark_debug = "true" *) wire [3:0]m01_axi_arregion; wire [3:0]m01_axi_arregion;
(* mark_debug = "true" *) wire [3:0]m01_axi_arqos; wire [3:0]m01_axi_arqos;
(* mark_debug = "true" *) wire m01_axi_arvalid; wire m01_axi_arvalid;
(* mark_debug = "true" *) wire m01_axi_arready; wire m01_axi_arready;
(* mark_debug = "true" *) wire [3:0] m01_axi_rid; wire [3:0] m01_axi_rid;
(* mark_debug = "true" *) wire [63:0]m01_axi_rdata; wire [63:0]m01_axi_rdata;
(* mark_debug = "true" *) wire [1:0]m01_axi_rresp; wire [1:0]m01_axi_rresp;
(* mark_debug = "true" *) wire m01_axi_rlast; wire m01_axi_rlast;
(* mark_debug = "true" *) wire m01_axi_rvalid; wire m01_axi_rvalid;
(* mark_debug = "true" *) wire m01_axi_rready; wire m01_axi_rready;
// Old SDC input // Old SDC input
// wire [3:0] SDCDatIn; // wire [3:0] SDCDatIn;
@ -401,7 +405,7 @@ module fpgaTop
wire sd_cmd_reg_t; wire sd_cmd_reg_t;
// SD Card Interrupt signal // SD Card Interrupt signal
(* mark_debug = "true" *) wire SDCIntr; wire SDCIntr;
// New SDC Data IOBUF connections // New SDC Data IOBUF connections
wire [3:0] sd_dat_i; wire [3:0] sd_dat_i;
@ -409,10 +413,10 @@ module fpgaTop
wire sd_dat_reg_t; wire sd_dat_reg_t;
(* mark_debug = "true" *) wire c0_init_calib_complete; wire c0_init_calib_complete;
wire dbg_clk; wire dbg_clk;
wire [511 : 0] dbg_bus; wire [511 : 0] dbg_bus;
(* mark_debug = "true" *) wire ui_clk_sync_rst; wire ui_clk_sync_rst;
wire CLK208; wire CLK208;
wire clk167; wire clk167;
@ -421,9 +425,9 @@ module fpgaTop
wire app_sr_active; wire app_sr_active;
wire app_ref_ack; wire app_ref_ack;
wire app_zq_ack; wire app_zq_ack;
(* mark_debug = "true" *) wire mmcm_locked; wire mmcm_locked;
wire [11:0] device_temp; wire [11:0] device_temp;
(* mark_debug = "true" *) wire mmcm1_locked; wire mmcm1_locked;
assign GPIOIN = {28'b0, GPI}; assign GPIOIN = {28'b0, GPI};
@ -470,7 +474,7 @@ module fpgaTop
// reset controller XILINX IP // reset controller XILINX IP
xlnx_proc_sys_reset xlnx_proc_sys_reset_0 xlnx_proc_sys_reset xlnx_proc_sys_reset_0
(.slowest_sync_clk(CPUCLK), (.slowest_sync_clk(CPUCLK),
.ext_reset_in(c0_ddr4_ui_clk_sync_rst), .ext_reset_in(1'b0),
.aux_reset_in(south_reset), .aux_reset_in(south_reset),
.mb_debug_sys_rst(1'b0), .mb_debug_sys_rst(1'b0),
.dcm_locked(c0_init_calib_complete), .dcm_locked(c0_init_calib_complete),
@ -482,47 +486,18 @@ module fpgaTop
// wally // wally
// *** FIXME add sdc interrupt and HSELEXTSDC, remove old sdc // *** FIXME add sdc interrupt and HSELEXTSDC, remove old sdc
wallypipelinedsocwrapper wallypipelinedsocwrapper
(.clk(CPUCLK), `include "parameter-defs.vh"
.reset_ext(bus_struct_reset),
.reset(), wallypipelinedsoc #(P)
// bus interface wallypipelinedsoc(.clk(CPUCLK), .reset_ext(bus_struct_reset), .reset(),
.HRDATAEXT(HRDATAEXT), .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT,
.HREADYEXT(HREADYEXT), .HSELEXTSDC, .HCLK(HCLKOpen), .HRESETn(HRESETnOpen),
.HRESPEXT(HRESPEXT), .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
.HSELEXT(HSELEXT), .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0),
.HSELEXTSDC(HSELEXTSDC), .GPIOIN, .GPIOOUT, .GPIOEN,
.HCLK(HCLKOpen), // open .UARTSin, .UARTSout, .SDCIntr);
.HRESETn(HRESETnOpen), // open
.HADDR(HADDR),
.HWDATA(HWDATA),
.HWSTRB(HWSTRB),
.HWRITE(HWRITE),
.HSIZE(HSIZE),
.HBURST(HBURST),
.HPROT(HPROT),
.HTRANS(HTRANS),
.HMASTLOCK(HMASTLOCK),
.HREADY(HREADY),
// MTIME
.TIMECLK(1'b0),
// GPIO
.GPIOIN(GPIOIN),
.GPIOOUT(GPIOOUT),
.GPIOEN(GPIOEN),
// UART
.UARTSin(UARTSin),
.UARTSout(UARTSout),
.SDCIntr(SDCIntr)
// SD Card
/* -----\/----- EXCLUDED -----\/-----
.SDCDatIn(SDCDat),
.SDCCmdIn(SDCCmdIn),
.SDCCmdOut(SDCCmdOut),
.SDCCmdOE(SDCCmdOE),
.SDCCLK(SDCCLK));
-----/\----- EXCLUDED -----/\----- */
);
// ahb lite to axi bridge // ahb lite to axi bridge
xlnx_ahblite_axi_bridge xlnx_ahblite_axi_bridge_0 xlnx_ahblite_axi_bridge xlnx_ahblite_axi_bridge_0

2
src/ieu/controller.sv
View File

@ -431,6 +431,6 @@ module controller import cvw::*; #(parameter cvw_t P) (
// *** RT: Check that atomic after atomic works correctly. // *** RT: Check that atomic after atomic works correctly.
//assign StoreStallD = ((|CMOpE)) & ((|CMOpD)); //assign StoreStallD = ((|CMOpE)) & ((|CMOpD));
logic AMOHazard; logic AMOHazard;
assign AMOHazard = &MemRWM & MemRWE[1]; assign AMOHazard = &MemRWE & MemRWD[1];
assign StoreStallD = ((|CMOpE) & (|CMOpD)) | AMOHazard; assign StoreStallD = ((|CMOpE) & (|CMOpD)) | AMOHazard;
endmodule endmodule