diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv
index dd7b9e850..485875b66 100644
--- a/pipelined/src/ifu/brpred/bpred.sv
+++ b/pipelined/src/ifu/brpred/bpred.sv
@@ -146,7 +146,6 @@ module bpred (
           .UpdateEN(|InstrClassE | PredictionInstrClassWrongE),
           .PCE,
           .IEUAdrE,
-          .UpdateInvalid(PredictionInstrClassWrongE),
           .InstrClassE);
 
   // Part 3 RAS
diff --git a/pipelined/src/ifu/brpred/btb.sv b/pipelined/src/ifu/brpred/btb.sv
index bcf5dcfd9..aba3826b3 100644
--- a/pipelined/src/ifu/brpred/btb.sv
+++ b/pipelined/src/ifu/brpred/btb.sv
@@ -44,8 +44,7 @@ module btb
    input  logic             UpdateEN,
    input  logic [`XLEN-1:0] PCE,
    input  logic [`XLEN-1:0] IEUAdrE,
-   input  logic [3:0]       InstrClassE,
-   input  logic             UpdateInvalid
+   input  logic [3:0]       InstrClassE
    );
 
   localparam TotalDepth = 2 ** Depth;
@@ -92,7 +91,7 @@ module btb
     if (reset) begin
       ValidBits <= #1 {TotalDepth{1'b0}};
     end else if (UpdateEN & ~StallM & ~FlushM) begin
-      ValidBits[PCEIndex] <= #1 ~ UpdateInvalid;
+      ValidBits[PCEIndex] <= #1 |InstrClassE;
     end
 	PredValidF = ValidBits[PCNextFIndex];
   end