Moved writeback pipeline registers from datapth into DMEM and CSR

wally-pipelined/src/dmem/dmem.sv

@@ -29,21 +29,25 @@
 
 module dmem (
   input  logic            clk, reset,
+  input  logic            FlushW,
   //
   input  logic [1:0]      MemRWM,
   output logic [1:0]      MemRWdcuoutM,
   output logic            DataMisalignedM,
 
   input  logic [`XLEN-1:0] DataAdrM,
-  input  logic [2:0]      Funct3M,
+  input  logic [2:0]       Funct3M,
-/*  output  logic [`XLEN-1:0] ReadDataM,
+  input  logic [`XLEN-1:0] ReadDataM,
-  input logic [`XLEN-1:0] WriteDataM, */
+  output logic [`XLEN-1:0] ReadDataW,
+/*  input logic [`XLEN-1:0] WriteDataM, */
   // faults
   input  logic            DataAccessFaultM,
   output logic            LoadMisalignedFaultM, LoadAccessFaultM,
   output logic            StoreMisalignedFaultM, StoreAccessFaultM
 );
 
+  // Pipeline register       
+  floprc #(`XLEN) ReadDataWReg(clk, reset, FlushW, ReadDataM, ReadDataW);
 
 	// Determine if an Unaligned access is taking place
 	always_comb

wally-pipelined/src/ieu/controller.sv

@@ -82,6 +82,8 @@ module controller(
 	
 
   // Main Instruction Decoder
+  // *** decoding of non-IEU instructions should also go here, and should be gated by MISA bits in a generate so
+  // they don't get generated if that mode is disabled
   always_comb
     case(OpD)
     // RegWrite_ImmSrc_ALUSrc_MemRW_ResultSrc_Branch_ALUOp_Jump_TargetSrc_W64_CSRWrite_Privileged_Illegal

wally-pipelined/src/ieu/datapath.sv

@@ -44,8 +44,8 @@ module datapath (
   // Memory stage signals
   input  logic             FlushM,
   input  logic [2:0]       Funct3M,
-  input  logic [`XLEN-1:0] CSRReadValM,
+  input  logic [`XLEN-1:0] CSRReadValW,
-  input  logic [`XLEN-1:0] ReadDataM,
+  input  logic [`XLEN-1:0] ReadDataW,
   input  logic             RetM, TrapM,
   output logic [`XLEN-1:0] SrcAM,
   output logic [`XLEN-1:0] WriteDataM, DataAdrM,
@@ -75,8 +75,6 @@ module datapath (
   logic [`XLEN-1:0] ALUResultM;
   // Writeback stage signals
   logic [`XLEN-1:0] ALUResultW;
-  logic [`XLEN-1:0] ReadDataW;
-  logic [`XLEN-1:0] CSRValW;
   logic [`XLEN-1:0] ResultW;
 
   assign Rs1D      = InstrD[19:15];
@@ -111,9 +109,7 @@ module datapath (
   
   // Writeback stage pipeline register and logic
   floprc #(`XLEN) ALUResultWReg(clk, reset, FlushW, ALUResultM, ALUResultW);
-  floprc #(`XLEN) ReadDataWReg(clk, reset, FlushW, ReadDataM, ReadDataW);
-  floprc #(`XLEN) CSRValWReg(clk, reset, FlushW, CSRReadValM, CSRValW);
   floprc #(5)    RdWEg(clk, reset, FlushW, RdM, RdW);
 
-  mux4  #(`XLEN) resultmux(ALUResultW, ReadDataW, PCLinkW, CSRValW, ResultSrcW, ResultW);	
+  mux4  #(`XLEN) resultmux(ALUResultW, ReadDataW, PCLinkW, CSRReadValW, ResultSrcW, ResultW);	
 endmodule

wally-pipelined/src/ieu/ieu.sv

@@ -35,15 +35,15 @@ module ieu (
   input  logic [`XLEN-1:0] PCE, 
   output logic [`XLEN-1:0] PCTargetE,
   // Memory stage interface
-  input  logic [`XLEN-1:0] ReadDataM,
   input  logic             DataMisalignedM,
   input  logic             DataAccessFaultM,
-  input  logic [`XLEN-1:0] CSRReadValM,
   output logic [1:0]       MemRWM,
   output logic [`XLEN-1:0] DataAdrM, WriteDataM,
   output logic [`XLEN-1:0] SrcAM,
   output logic [2:0]       Funct3M,
   // Writeback stage
+  input  logic [`XLEN-1:0] ReadDataW,
+  input  logic [`XLEN-1:0] CSRReadValW,
   input  logic [`XLEN-1:0] PCLinkW,
   output logic             InstrValidW,
   // hazards

wally-pipelined/src/privileged/csr.sv

@@ -28,6 +28,7 @@
 
 module csr (
   input  logic             clk, reset,
+  input  logic             FlushW,
   input  logic [31:0]      InstrM, 
   input  logic [`XLEN-1:0] PCM, SrcAM,
   input  logic             CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, uretM,
@@ -44,11 +45,11 @@ module csr (
   input  logic [4:0]       SetFflagsM,
   output logic [2:0]       FRM_REGW, 
 //  output logic [11:0]     MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW,
-  output logic [`XLEN-1:0] CSRReadValM,
+  output logic [`XLEN-1:0] CSRReadValW,
   output logic             IllegalCSRAccessM
 );
 
-  logic [`XLEN-1:0] CSRMReadValM, CSRSReadValM, CSRUReadValM, CSRNReadValM, CSRCReadValM;
+  logic [`XLEN-1:0] CSRMReadValM, CSRSReadValM, CSRUReadValM, CSRNReadValM, CSRCReadValM, CSRReadValM;
   logic [`XLEN-1:0] CSRSrcM, CSRRWM, CSRRSM, CSRRCM, CSRWriteValM;
  
   logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, USTATUS_REGW;
@@ -101,6 +102,7 @@ module csr (
 
       // merge CSR Reads
       assign CSRReadValM = CSRUReadValM | CSRSReadValM | CSRMReadValM | CSRCReadValM | CSRNReadValM; 
+      floprc #(`XLEN) CSRValWReg(clk, reset, FlushW, CSRReadValM, CSRReadValW);
 
       // merge illegal accesses: illegal if none of the CSR addresses is legal or privilege is insufficient
       assign InsufficientCSRPrivilegeM = (CSRAdrM[9:8] == 2'b11 && PrivilegeModeW != `M_MODE) ||

wally-pipelined/src/privileged/privileged.sv

@@ -28,11 +28,12 @@
 
 module privileged (
   input  logic             clk, reset,
+  input  logic             FlushW,
   input  logic             CSRWriteM,
   input  logic [`XLEN-1:0] SrcAM,
   input  logic [31:0]      InstrM,
   input  logic [`XLEN-1:0] PCM,
-  output logic [`XLEN-1:0] CSRReadValM,
+  output logic [`XLEN-1:0] CSRReadValW,
   output logic [`XLEN-1:0] PrivilegedNextPCM,
   output logic             RetM, TrapM,
   input  logic             InstrValidW, FloatRegWriteW, LoadStallD,

wally-pipelined/src/wally/wallypipelinedhart.sv

@@ -59,7 +59,7 @@ module wallypipelinedhart (
   logic [31:0] InstrD, InstrM;
   logic [`XLEN-1:0] PCE, PCM, PCLinkW;
   logic [`XLEN-1:0] PCTargetE;
-  logic [`XLEN-1:0] CSRReadValM;
+  logic [`XLEN-1:0] CSRReadValW;
   logic [`XLEN-1:0] PrivilegedNextPCM;
   logic [1:0] MemRWM;
   logic InstrValidW;
@@ -83,11 +83,11 @@ module wallypipelinedhart (
   logic [2:0] FRM_REGW;
   logic       FloatRegWriteW;
 
-  // bus interface to dcu
+  // bus interface to dmem
   logic [1:0]      MemRWdcuoutM;
   logic [2:0]      Funct3M;
   logic [`XLEN-1:0] DataAdrM, WriteDataM;
-  logic [`XLEN-1:0] ReadDataM;
+  logic [`XLEN-1:0] ReadDataM, ReadDataW;
   logic             DataStall, InstrStall;
            
   ifu ifu(.*); // instruction fetch unit: PC, branch prediction, instruction cache