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https://github.com/openhwgroup/cvw
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Resolved more lint errors in the rvvi synthesized hardware.
This commit is contained in:
Rose Thompson
parent
94a1ce32e7
commit
bb74a0f96b
77
src/rvvi/csrindextoaddr.sv
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77
src/rvvi/csrindextoaddr.sv
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///////////////////////////////////////////
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// csrindextoaddr.sv
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//
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// Written: Rose Thompson ross1728@gmail.com
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// Created: 24 January 2024
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// Modified: 24 January 2024
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//
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// Purpose: Converts the rvvi CSR index into the CSR address
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//
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// Documentation:
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module csrindextoaddr #(parameter TOTAL_CSRS = 36) (
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input logic [TOTAL_CSRS-1:0] CSRWen,
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output logic [11:0] CSRAddr);
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always_comb begin
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case(CSRWen)
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36'h0_0000_0000: CSRAddr = 12'h000;
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36'h0_0000_0001: CSRAddr = 12'h300;
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36'h0_0000_0002: CSRAddr = 12'h310;
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36'h0_0000_0004: CSRAddr = 12'h305;
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36'h0_0000_0008: CSRAddr = 12'h341;
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36'h0_0000_0010: CSRAddr = 12'h306;
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36'h0_0000_0020: CSRAddr = 12'h320;
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36'h0_0000_0040: CSRAddr = 12'h302;
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36'h0_0000_0080: CSRAddr = 12'h303;
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36'h0_0000_0100: CSRAddr = 12'h344;
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36'h0_0000_0200: CSRAddr = 12'h304;
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36'h0_0000_0400: CSRAddr = 12'h301;
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36'h0_0000_0800: CSRAddr = 12'h30A;
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36'h0_0000_1000: CSRAddr = 12'hF14;
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36'h0_0000_2000: CSRAddr = 12'h340;
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36'h0_0000_4000: CSRAddr = 12'h342;
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36'h0_0000_8000: CSRAddr = 12'h343;
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36'h0_0001_0000: CSRAddr = 12'hF11;
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36'h0_0002_0000: CSRAddr = 12'hF12;
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36'h0_0004_0000: CSRAddr = 12'hF13;
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36'h0_0008_0000: CSRAddr = 12'hF15;
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36'h0_0010_0000: CSRAddr = 12'h34A;
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36'h0_0020_0000: CSRAddr = 12'h100;
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36'h0_0040_0000: CSRAddr = 12'h104;
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36'h0_0080_0000: CSRAddr = 12'h105;
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36'h0_0100_0000: CSRAddr = 12'h141;
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36'h0_0200_0000: CSRAddr = 12'h106;
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36'h0_0400_0000: CSRAddr = 12'h10A;
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36'h0_0800_0000: CSRAddr = 12'h180;
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36'h0_1000_0000: CSRAddr = 12'h140;
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36'h0_2000_0000: CSRAddr = 12'h143;
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36'h0_4000_0000: CSRAddr = 12'h142;
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36'h0_8000_0000: CSRAddr = 12'h144;
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36'h1_0000_0000: CSRAddr = 12'h14D;
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36'h2_0000_0000: CSRAddr = 12'h001;
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36'h4_0000_0000: CSRAddr = 12'h002;
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36'h8_0000_0000: CSRAddr = 12'h003;
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default : CSRAddr = 12'h000;
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endcase
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end
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endmodule
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@ -129,7 +129,7 @@ module packetizer import cvw::*; #(parameter cvw_t P,
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assign Tag = 32'b0;
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assign Tag = 32'b0;
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assign EthType = 16'h005c;
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assign EthType = 16'h005c;
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assign RvviAxiWdata = TotalFrameWords[WordCount];
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assign RvviAxiWdata = TotalFrameWords[WordCount[4:0]];
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assign RvviAxiWstrb = '1;
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assign RvviAxiWstrb = '1;
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assign RvviAxiWlast = BurstDone & (CurrState == STATE_TRANS);
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assign RvviAxiWlast = BurstDone & (CurrState == STATE_TRANS);
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assign RvviAxiWvalid = (CurrState == STATE_TRANS);
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assign RvviAxiWvalid = (CurrState == STATE_TRANS);
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@ -1,77 +0,0 @@
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///////////////////////////////////////////
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// csrindextoaddr.sv
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//
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// Written: Rose Thompson ross1728@gmail.com
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// Created: 24 January 2024
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// Modified: 24 January 2024
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//
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// Purpose: Converts the rvvi CSR index into the CSR address
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//
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// Documentation:
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module csrindextoaddr #(parameter TOTAL_CSRS = 36) (
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input logic [TOTAL_CSRS-1:0] CSRWen,
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output logic [11:0] CSRAddr);
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always_comb begin
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case(CSRWen)
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36'h0_0000_0000: CSRAddr = 13'h000;
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36'h0_0000_0001: CSRAddr = 13'h300;
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36'h0_0000_0002: CSRAddr = 13'h310;
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36'h0_0000_0004: CSRAddr = 13'h305;
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36'h0_0000_0008: CSRAddr = 13'h341;
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36'h0_0000_0010: CSRAddr = 13'h306;
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36'h0_0000_0020: CSRAddr = 13'h320;
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36'h0_0000_0040: CSRAddr = 13'h302;
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36'h0_0000_0080: CSRAddr = 13'h303;
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36'h0_0000_0100: CSRAddr = 13'h344;
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36'h0_0000_0200: CSRAddr = 13'h304;
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36'h0_0000_0400: CSRAddr = 13'h301;
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36'h0_0000_0800: CSRAddr = 13'h30A;
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36'h0_0000_1000: CSRAddr = 13'hF14;
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36'h0_0000_2000: CSRAddr = 13'h340;
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36'h0_0000_4000: CSRAddr = 13'h342;
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36'h0_0000_8000: CSRAddr = 13'h343;
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36'h0_0001_0000: CSRAddr = 13'hF11;
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36'h0_0002_0000: CSRAddr = 13'hF12;
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36'h0_0004_0000: CSRAddr = 13'hF13;
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36'h0_0008_0000: CSRAddr = 13'hF15;
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36'h0_0010_0000: CSRAddr = 13'h34A;
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36'h0_0020_0000: CSRAddr = 13'h100;
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36'h0_0040_0000: CSRAddr = 13'h104;
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36'h0_0080_0000: CSRAddr = 13'h105;
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36'h0_0100_0000: CSRAddr = 13'h141;
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36'h0_0200_0000: CSRAddr = 13'h106;
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36'h0_0400_0000: CSRAddr = 13'h10A;
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36'h0_0800_0000: CSRAddr = 13'h180;
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36'h0_1000_0000: CSRAddr = 13'h140;
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36'h0_2000_0000: CSRAddr = 13'h143;
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36'h0_4000_0000: CSRAddr = 13'h142;
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36'h0_8000_0000: CSRAddr = 13'h144;
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36'h1_0000_0000: CSRAddr = 13'h14D;
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36'h2_0000_0000: CSRAddr = 13'h001;
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36'h4_0000_0000: CSRAddr = 13'h002;
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36'h8_0000_0000: CSRAddr = 13'h003;
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default : CSRAddr = 13'h000;
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endcase
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end
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endmodule
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