Modified the preformance counter's InstRet to include ECALL and EBREAK by changing the hazard logic so these instructions don't self flush the W stage.

wally-pipelined/src/hazard/hazard.sv

@@ -34,6 +34,7 @@ module hazard(
 	      input logic  LSUStall, ICacheStallF,
               input logic  FPUStallD, FStallD,
 	      input logic  DivBusyE,FDivBusyE,
+	      input logic  EcallFaultM, BreakpointFaultM,
   // Stall & flush outputs
 	      output logic StallF, StallD, StallE, StallM, StallW,
 	      output logic FlushF, FlushD, FlushE, FlushM, FlushW
@@ -79,5 +80,7 @@ module hazard(
   assign FlushD = FirstUnstalledD | TrapM | RetM | BPPredWrongE;
   assign FlushE = FirstUnstalledE | TrapM | RetM | BPPredWrongE;
   assign FlushM = FirstUnstalledM | TrapM | RetM;
-  assign FlushW = FirstUnstalledW | TrapM;
+  // on Trap the memory stage should be flushed going into the W stage,
+  // except if the instruction causing the Trap is an ecall or ebreak.
+  assign FlushW = FirstUnstalledW | (TrapM & ~(BreakpointFaultM | EcallFaultM));
 endmodule

wally-pipelined/src/privileged/privileged.sv

@@ -75,7 +75,9 @@ module privileged (
   output logic  [1:0]      STATUS_MPP,
   output var logic [7:0]   PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
   output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], 
-  output logic [2:0]       FRM_REGW
+  output logic [2:0]       FRM_REGW,
+  output logic             BreakpointFaultM, EcallFaultM
+
 );
 
   logic [1:0] NextPrivilegeModeM;
@@ -94,7 +96,6 @@ module privileged (
   logic InstrAccessFaultD, InstrAccessFaultE, InstrAccessFaultM;
   logic IllegalInstrFaultM, TrappedSRETM;
 
-  logic BreakpointFaultM, EcallFaultM;
   logic MTrapM, STrapM, UTrapM;
   logic InterruptM; 
 

wally-pipelined/src/wally/wallypipelinedhart.sv

@@ -167,6 +167,7 @@ module wallypipelinedhart
   logic 		    PendingInterruptM;
   logic 		    DCacheMiss;
   logic 		    DCacheAccess;
+  logic 		    BreakpointFaultM, EcallFaultM;
 
   
   ifu ifu(.InstrInF(InstrRData),