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added individual zb tests in tests.vh and testbench

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- also minor alu/controller configurability changes
This commit is contained in:
Kevin Kim 2023-02-21 11:52:05 -08:00
parent 73833d5576
commit bb252acfbe
4 changed files with 186 additions and 114 deletions
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4
src/ieu/alu.sv
View File

@ -106,7 +106,7 @@ module alu #(parameter WIDTH=32) (
assign SLTU = {{(WIDTH-1){1'b0}}, LTU}; assign SLTU = {{(WIDTH-1){1'b0}}, LTU};
// Select appropriate ALU Result // Select appropriate ALU Result
if (`ZBS_SUPPORTED) begin if (`ZBS_SUPPORTED | `ZBB_SUPPORTED) begin
always_comb always_comb
if (~ALUOp) FullResult = Sum; // Always add for ALUOp = 0 (address generation) if (~ALUOp) FullResult = Sum; // Always add for ALUOp = 0 (address generation)
else casez (ALUSelect) // Otherwise check Funct3 NOTE: change signal name to ALUSelect else casez (ALUSelect) // Otherwise check Funct3 NOTE: change signal name to ALUSelect
@ -150,7 +150,7 @@ module alu #(parameter WIDTH=32) (
end else assign ZBBResult = 0; end else assign ZBBResult = 0;
// Final Result B instruction select mux // Final Result B instruction select mux
if (`ZBC_SUPPORTED | `ZBS_SUPPORTED) begin : zbdecoder if (`ZBC_SUPPORTED | `ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED) begin : zbdecoder
always_comb always_comb
case (BSelect) case (BSelect)
//ZBA_ZBB_ZBC_ZBS //ZBA_ZBB_ZBC_ZBS

2
src/ieu/controller.sv
View File

@ -239,7 +239,7 @@ module controller(
assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand
assign ALUControlD = {W64D, SubArithD, ALUOpD}; assign ALUControlD = {W64D, SubArithD, ALUOpD};
if (`ZBS_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags
bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE); bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE);
end else begin: bitmanipi end else begin: bitmanipi
assign ALUSelectD = Funct3D; assign ALUSelectD = Funct3D;

9
testbench/testbench.sv
View File

@ -105,6 +105,10 @@ logic [3:0] dummy;
"coremark": tests = coremark; "coremark": tests = coremark;
"fpga": tests = fpga; "fpga": tests = fpga;
"ahb" : tests = ahb; "ahb" : tests = ahb;
"arch64zba": if (`ZBA_SUPPORTED) tests = arch64zba;
"arch64zbb": if (`ZBB_SUPPORTED) tests = arch64zbb;
"arch64zbc": if (`ZBC_SUPPORTED) tests = arch64zbc;
"arch64zbs": if (`ZBS_SUPPORTED) tests = arch64zbs;
"arch64b": if (`ZBB_SUPPORTED & `ZBA_SUPPORTED & `ZBS_SUPPORTED & `ZBC_SUPPORTED) tests = arch64b; "arch64b": if (`ZBB_SUPPORTED & `ZBA_SUPPORTED & `ZBS_SUPPORTED & `ZBC_SUPPORTED) tests = arch64b;
endcase endcase
end else begin // RV32 end else begin // RV32
@ -130,7 +134,10 @@ logic [3:0] dummy;
"wally32periph": tests = wally32periph; "wally32periph": tests = wally32periph;
"embench": tests = embench; "embench": tests = embench;
"coremark": tests = coremark; "coremark": tests = coremark;
"arch32ba": if (`ZBA_SUPPORTED) tests = arch32ba; "arch32zba": if (`ZBA_SUPPORTED) tests = arch32zba;
"arch32zbb": if (`ZBB_SUPPORTED) tests = arch32zbb;
"arch32zbc": if (`ZBC_SUPPORTED) tests = arch32zbc;
"arch32zbs": if (`ZBS_SUPPORTED) tests = arch32zbs;
"arch32b": if (`ZBB_SUPPORTED & `ZBA_SUPPORTED & `ZBS_SUPPORTED & `ZBC_SUPPORTED) tests = arch32b; "arch32b": if (`ZBB_SUPPORTED & `ZBA_SUPPORTED & `ZBS_SUPPORTED & `ZBC_SUPPORTED) tests = arch32b;
endcase endcase
end end

277
testbench/tests.vh
View File

@ -881,12 +881,126 @@ string imperas32f[] = '{
"rv32i_m/Zifencei/src/Fencei.S" "rv32i_m/Zifencei/src/Fencei.S"
}; };
string arch32ba[] = '{ string arch32zba[] = '{
`RISCVARCHTEST, `RISCVARCHTEST,
// *** unclear why add.uw isn't in the list
"rv32i_m/B/src/sh1add-01.S", "rv32i_m/B/src/sh1add-01.S",
"rv32i_m/B/src/sh1add-02.S", "rv32i_m/B/src/sh2add-01.S",
"rv32i_m/B/src/sh1add-013.S" "rv32i_m/B/src/sh3add-01.S"
};
string arch32zbb[] = '{
`RISCVARCHTEST,
"rv32i_m/B/src/max-01.S",
"rv32i_m/B/src/maxu-01.S",
"rv32i_m/B/src/min-01.S",
"rv32i_m/B/src/minu-01.S",
"rv32i_m/B/src/orcb_32-01.S",
"rv32i_m/B/src/rev8_32-01.S",
"rv32i_m/B/src/andn-01.S",
"rv32i_m/B/src/orn-01.S",
"rv32i_m/B/src/xnor-01.S",
"rv32i_m/B/src/zext.h_32-01.S",
"rv32i_m/B/src/sext.b-01.S",
"rv32i_m/B/src/sext.h-01.S",
"rv32i_m/B/src/clz-01.S",
"rv32i_m/B/src/cpop-01.S",
"rv32i_m/B/src/ctz-01.S",
"rv32i_m/B/src/ror-01.S",
"rv32i_m/B/src/rori-01.S",
"rv32i_m/B/src/rol-01.S"
};
string arch32zbc[] = '{
`RISCVARCHTEST,
"rv32i_m/B/src/clmul-01.S",
"rv32i_m/B/src/clmulh-01.S",
"rv32i_m/B/src/clmulr-01.S"
};
string arch32zbs[] = '{
`RISCVARCHTEST,
"rv32i_m/B/src/bclr-01.S",
"rv32i_m/B/src/bclri-01.S",
"rv32i_m/B/src/bext-01.S",
"rv32i_m/B/src/bexti-01.S",
"rv32i_m/B/src/binv-01.S",
"rv32i_m/B/src/binvi-01.S",
"rv32i_m/B/src/bset-01.S",
"rv32i_m/B/src/bseti-01.S"
};
string arch32b[] = '{
`RISCVARCHTEST,
"rv32i_m/B/src/clmul-01.S",
"rv32i_m/B/src/clmulh-01.S",
"rv32i_m/B/src/clmulr-01.S",
"rv32i_m/B/src/bclr-01.S",
"rv32i_m/B/src/bclri-01.S",
"rv32i_m/B/src/bext-01.S",
"rv32i_m/B/src/bexti-01.S",
"rv32i_m/B/src/binv-01.S",
"rv32i_m/B/src/binvi-01.S",
"rv32i_m/B/src/bset-01.S",
"rv32i_m/B/src/bseti-01.S",
"rv32i_m/B/src/max-01.S",
"rv32i_m/B/src/maxu-01.S",
"rv32i_m/B/src/min-01.S",
"rv32i_m/B/src/minu-01.S",
"rv32i_m/B/src/orcb_32-01.S",
"rv32i_m/B/src/rev8_32-01.S",
"rv32i_m/B/src/andn-01.S",
"rv32i_m/B/src/orn-01.S",
"rv32i_m/B/src/xnor-01.S",
"rv32i_m/B/src/zext.h_32-01.S",
"rv32i_m/B/src/sext.b-01.S",
"rv32i_m/B/src/sext.h-01.S",
"rv32i_m/B/src/clz-01.S",
"rv32i_m/B/src/cpop-01.S",
"rv32i_m/B/src/ctz-01.S",
"rv32i_m/B/src/ror-01.S",
"rv32i_m/B/src/rori-01.S",
"rv32i_m/B/src/rol-01.S",
"rv32i_m/B/src/sh1add-01.S",
"rv32i_m/B/src/sh2add-01.S",
"rv32i_m/B/src/sh3add-01.S",
"rv32i_m/I/src/add-01.S",
"rv32i_m/I/src/addi-01.S",
"rv32i_m/I/src/and-01.S",
"rv32i_m/I/src/andi-01.S",
"rv32i_m/I/src/auipc-01.S",
"rv32i_m/I/src/beq-01.S",
"rv32i_m/I/src/bge-01.S",
"rv32i_m/I/src/bgeu-01.S",
"rv32i_m/I/src/blt-01.S",
"rv32i_m/I/src/bltu-01.S",
"rv32i_m/I/src/bne-01.S",
"rv32i_m/I/src/fence-01.S",
"rv32i_m/I/src/jal-01.S",
"rv32i_m/I/src/jalr-01.S",
"rv32i_m/I/src/lb-align-01.S",
"rv32i_m/I/src/lbu-align-01.S",
"rv32i_m/I/src/lh-align-01.S",
"rv32i_m/I/src/lhu-align-01.S",
"rv32i_m/I/src/lui-01.S",
"rv32i_m/I/src/lw-align-01.S",
"rv32i_m/I/src/or-01.S",
"rv32i_m/I/src/ori-01.S",
"rv32i_m/I/src/sb-align-01.S",
"rv32i_m/I/src/sh-align-01.S",
"rv32i_m/I/src/sll-01.S",
"rv32i_m/I/src/slli-01.S",
"rv32i_m/I/src/slt-01.S",
"rv32i_m/I/src/slti-01.S",
"rv32i_m/I/src/sltiu-01.S",
"rv32i_m/I/src/sltu-01.S",
"rv32i_m/I/src/sra-01.S",
"rv32i_m/I/src/srai-01.S",
"rv32i_m/I/src/srl-01.S",
"rv32i_m/I/src/srli-01.S",
"rv32i_m/I/src/sub-01.S",
"rv32i_m/I/src/sw-align-01.S",
"rv32i_m/I/src/xor-01.S",
"rv32i_m/I/src/xori-01.S"
}; };
string arch64m[] = '{ string arch64m[] = '{
@ -1422,101 +1536,59 @@ string arch64b[] = '{
"rv64i_m/B/src/binvi-01.S", "rv64i_m/B/src/binvi-01.S",
"rv64i_m/B/src/bset-01.S", "rv64i_m/B/src/bset-01.S",
"rv64i_m/B/src/bseti-01.S" "rv64i_m/B/src/bseti-01.S"
/*"rv64i_m/B/src/add.uw-01.S",
"rv64i_m/B/src/bclr-01.S",
"rv64i_m/B/src/bclri-01.S",
"rv64i_m/B/src/bext-01.S",
"rv64i_m/B/src/bexti-01.S",
"rv64i_m/B/src/binv-01.S",
"rv64i_m/B/src/binvi-01.S",
"rv64i_m/B/src/bset-01.S",
"rv64i_m/B/src/bseti-01.S",
"rv64i_m/B/src/clmul-01.S",
"rv64i_m/B/src/rol-01.S",
*/
}; };
string arch32b[] = '{ string arch64zba[] = '{
`RISCVARCHTEST, `RISCVARCHTEST,
"rv32i_m/B/src/clmul-01.S", "rv64i_m/B/src/slli.uw-01.S",
"rv32i_m/B/src/clmulh-01.S", "rv64i_m/B/src/add.uw-01.S",
"rv32i_m/B/src/clmulr-01.S", "rv64i_m/B/src/sh1add-01.S",
"rv32i_m/B/src/bclr-01.S", "rv64i_m/B/src/sh2add-01.S",
"rv32i_m/B/src/bclri-01.S", "rv64i_m/B/src/sh3add-01.S",
"rv32i_m/B/src/bext-01.S", "rv64i_m/B/src/sh1add.uw-01.S",
"rv32i_m/B/src/bexti-01.S", "rv64i_m/B/src/sh2add.uw-01.S",
"rv32i_m/B/src/binv-01.S", "rv64i_m/B/src/sh3add.uw-01.S"
"rv32i_m/B/src/binvi-01.S", };
"rv32i_m/B/src/bset-01.S",
"rv32i_m/B/src/bseti-01.S",
"rv32i_m/B/src/max-01.S",
"rv32i_m/B/src/maxu-01.S",
"rv32i_m/B/src/min-01.S",
"rv32i_m/B/src/minu-01.S",
"rv32i_m/B/src/orcb_32-01.S",
"rv32i_m/B/src/rev8_32-01.S",
"rv32i_m/B/src/andn-01.S",
"rv32i_m/B/src/orn-01.S",
"rv32i_m/B/src/xnor-01.S",
"rv32i_m/B/src/zext.h_32-01.S",
"rv32i_m/B/src/sext.b-01.S",
"rv32i_m/B/src/sext.h-01.S",
"rv32i_m/B/src/clz-01.S",
"rv32i_m/B/src/cpop-01.S",
"rv32i_m/B/src/ctz-01.S",
"rv32i_m/B/src/ror-01.S",
"rv32i_m/B/src/rori-01.S",
"rv32i_m/B/src/rol-01.S",
"rv32i_m/B/src/sh1add-01.S",
"rv32i_m/B/src/sh2add-01.S",
"rv32i_m/B/src/sh3add-01.S",
"rv32i_m/I/src/add-01.S",
"rv32i_m/I/src/addi-01.S",
"rv32i_m/I/src/and-01.S",
"rv32i_m/I/src/andi-01.S",
"rv32i_m/I/src/auipc-01.S",
"rv32i_m/I/src/beq-01.S",
"rv32i_m/I/src/bge-01.S",
"rv32i_m/I/src/bgeu-01.S",
"rv32i_m/I/src/blt-01.S",
"rv32i_m/I/src/bltu-01.S",
"rv32i_m/I/src/bne-01.S",
"rv32i_m/I/src/fence-01.S",
"rv32i_m/I/src/jal-01.S",
"rv32i_m/I/src/jalr-01.S",
"rv32i_m/I/src/lb-align-01.S",
"rv32i_m/I/src/lbu-align-01.S",
"rv32i_m/I/src/lh-align-01.S",
"rv32i_m/I/src/lhu-align-01.S",
"rv32i_m/I/src/lui-01.S",
"rv32i_m/I/src/lw-align-01.S",
"rv32i_m/I/src/or-01.S",
"rv32i_m/I/src/ori-01.S",
"rv32i_m/I/src/sb-align-01.S",
"rv32i_m/I/src/sh-align-01.S",
"rv32i_m/I/src/sll-01.S",
"rv32i_m/I/src/slli-01.S",
"rv32i_m/I/src/slt-01.S",
"rv32i_m/I/src/slti-01.S",
"rv32i_m/I/src/sltiu-01.S",
"rv32i_m/I/src/sltu-01.S",
"rv32i_m/I/src/sra-01.S",
"rv32i_m/I/src/srai-01.S",
"rv32i_m/I/src/srl-01.S",
"rv32i_m/I/src/srli-01.S",
"rv32i_m/I/src/sub-01.S",
"rv32i_m/I/src/sw-align-01.S",
"rv32i_m/I/src/xor-01.S",
"rv32i_m/I/src/xori-01.S"
/*"rv64i_m/B/src/add.uw-01.S",
string arch64zbb[] = '{
`RISCVARCHTEST,
"rv64i_m/B/src/max-01.S",
"rv64i_m/B/src/maxu-01.S",
"rv64i_m/B/src/min-01.S",
"rv64i_m/B/src/minu-01.S",
"rv64i_m/B/src/orcb_64-01.S",
"rv64i_m/B/src/rev8-01.S",
"rv64i_m/B/src/andn-01.S",
"rv64i_m/B/src/orn-01.S",
"rv64i_m/B/src/xnor-01.S",
"rv64i_m/B/src/zext.h-01.S",
"rv64i_m/B/src/sext.b-01.S",
"rv64i_m/B/src/sext.h-01.S",
"rv64i_m/B/src/clz-01.S",
"rv64i_m/B/src/clzw-01.S",
"rv64i_m/B/src/cpop-01.S",
"rv64i_m/B/src/cpopw-01.S",
"rv64i_m/B/src/ctz-01.S",
"rv64i_m/B/src/ctzw-01.S",
"rv64i_m/B/src/rolw-01.S",
"rv64i_m/B/src/ror-01.S",
"rv64i_m/B/src/rori-01.S",
"rv64i_m/B/src/roriw-01.S",
"rv64i_m/B/src/rorw-01.S",
"rv64i_m/B/src/rol-01.S"
};
string arch64zbc[] = '{
`RISCVARCHTEST,
"rv64i_m/B/src/clmul-01.S",
"rv64i_m/B/src/clmulh-01.S",
"rv64i_m/B/src/clmulr-01.S"
};
string arch64zbs[] = '{
`RISCVARCHTEST,
"rv64i_m/B/src/bclr-01.S", "rv64i_m/B/src/bclr-01.S",
"rv64i_m/B/src/bclri-01.S", "rv64i_m/B/src/bclri-01.S",
"rv64i_m/B/src/bext-01.S", "rv64i_m/B/src/bext-01.S",
@ -1524,18 +1596,11 @@ string arch32b[] = '{
"rv64i_m/B/src/binv-01.S", "rv64i_m/B/src/binv-01.S",
"rv64i_m/B/src/binvi-01.S", "rv64i_m/B/src/binvi-01.S",
"rv64i_m/B/src/bset-01.S", "rv64i_m/B/src/bset-01.S",
"rv64i_m/B/src/bseti-01.S", "rv64i_m/B/src/bseti-01.S"
"rv64i_m/B/src/clmul-01.S",
"rv64i_m/B/src/rol-01.S",
*/
}; };
string arch32priv[] = '{ string arch32priv[] = '{
`RISCVARCHTEST, `RISCVARCHTEST,
"rv32i_m/privilege/src/ebreak.S", "rv32i_m/privilege/src/ebreak.S",