From baff2c93626a68c2d1a9449c2de88b9381863823 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 18 Feb 2023 19:56:54 -0800 Subject: [PATCH] rotate instructions now handled in ZBB unit --- src/ieu/alu.sv | 3 ++- src/ieu/bmu/zbb.sv | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 696020593..164a2810a 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -145,7 +145,7 @@ module alu #(parameter WIDTH=32) ( end else assign ZBCResult = 0; if (`ZBB_SUPPORTED) begin: zbb - zbb #(WIDTH) ZBB(.A(A), .B(B), .W64(W64), .ZBBSelect(ZBBSelect), .ZBBResult(ZBBResult)); + zbb #(WIDTH) ZBB(.A(A), .B(B), .ALUResult(ALUResult), .W64(W64), .ZBBSelect(ZBBSelect), .ZBBResult(ZBBResult)); end else assign ZBBResult = 0; // Final Result B instruction select mux @@ -156,6 +156,7 @@ module alu #(parameter WIDTH=32) ( 4'b0001: Result = FullResult; 4'b0010: Result = ZBCResult; 4'b1000: Result = FullResult; // NOTE: We don't use ALUResult because ZBA instructions don't sign extend the MSB of the right-hand word. + 4'b0100: Result = ZBBResult; default: Result = ALUResult; endcase end else assign Result = ALUResult; diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 58cfccc5c..02591dd42 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -32,6 +32,7 @@ module zbb #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, B, // Operands + input logic [WIDTH-1:0] ALUResult, // ALU Result input logic W64, // Indicates word operation input logic [2:0] ZBBSelect, // Indicates word operation output logic [WIDTH-1:0] ZBBResult); // ZBB result @@ -57,6 +58,7 @@ module zbb #(parameter WIDTH=32) ( //can replace with structural mux by looking at bit 4 in rs2 field always_comb begin case (ZBBSelect) + 3'b111: ZBBResult = ALUResult; /*15'b0010100_101_00111: ZBBResult = OrcBResult; 15'b0110100_101_11000: ZBBResult = Rev8Result; 15'b0110101_101_11000: ZBBResult = Rev8Result;