mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
This commit is contained in:
Ross Thompson
commit
babcea195a
@ -31,7 +31,7 @@
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`define XLEN 64
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// MISA RISC-V configuration per specification
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`define MISA (32'h00000104 | 0 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
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`define MISA (32'h00000104 | 0 << 5 | 0 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
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`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
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`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
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`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
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@ -46,11 +46,7 @@ module fpu (
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output logic IllegalFPUInstrD,
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output logic [`XLEN-1:0] FPUResultW);
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//control logic signal instantiation
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// control logic signal instantiation
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logic FWriteEnD, FWriteEnE, FWriteEnM, FWriteEnW; // FP register write enable
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logic [2:0] FrmD, FrmE, FrmM, FrmW; // FP rounding mode
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logic FmtD, FmtE, FmtM, FmtW; // FP precision 0-single 1-double
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@ -142,7 +138,7 @@ module fpu (
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logic [63:0] FAddResultM, FAddResultW;
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logic [4:0] FAddFlagsM, FAddFlagsW;
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//cmp signals
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// cmp signals
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logic [7:0] WE, WM;
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logic [7:0] XE, XM;
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logic ANaNE, ANaNM;
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@ -157,14 +153,14 @@ module fpu (
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logic [63:0] SgnResultE, SgnResultM, SgnResultW;
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logic [4:0] SgnFlagsE, SgnFlagsM, SgnFlagsW;
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//instantiation of W stage regfile signals
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// instantiation of W stage regfile signals
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logic [`XLEN-1:0] SrcAW;
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// classify signals
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logic [63:0] ClassResultE, ClassResultM, ClassResultW;
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// other
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logic [63:0] FPUResult64W, FPUResult64E; // 64-bit FPU result
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// 64-bit FPU result
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logic [63:0] FPUResult64W, FPUResult64E;
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logic [4:0] FPUFlagsW;
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// pipeline control logic
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@ -175,65 +171,42 @@ module fpu (
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logic PipeClearEM;
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logic PipeClearMW;
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//temporarily assign pipe clear and enable signals
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//to never flush & always be running
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// temporarily assign pipe clear and enable signals
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// to never flush & always be running
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localparam PipeClear = 1'b0;
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localparam PipeEnable = 1'b1;
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always_comb begin
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PipeEnableDE = ~StallE;
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PipeEnableEM = ~StallM;
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PipeEnableMW = ~StallW;
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PipeClearDE = FlushE;
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PipeClearEM = FlushM;
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PipeClearMW = FlushW;
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end
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//DECODE STAGE
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//Hazard unit for FPU
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// Hazard unit for FPU
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fpuhazard hazard(.Adr1(InstrD[19:15]), .Adr2(InstrD[24:20]), .Adr3(InstrD[31:27]), .*);
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//top-level controller for FPU
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// top-level controller for FPU
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fctrl ctrl (.Funct7D(InstrD[31:25]), .OpD(InstrD[6:0]), .Rs2D(InstrD[24:20]), .Funct3D(InstrD[14:12]), .*);
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//regfile instantiation
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// regfile instantiation
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FPregfile fpregfile (clk, reset, FWriteEnW,
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InstrD[19:15], InstrD[24:20], InstrD[31:27], RdW,
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FPUResult64W,
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FRD1D, FRD2D, FRD3D);
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//*****************
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//fpregfile D/E pipe registers
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// fpregfile D/E pipe registers
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//*****************
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flopenrc #(64) DEReg1(clk, reset, PipeClearDE, PipeEnableDE, FRD1D, FRD1E);
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flopenrc #(64) DEReg2(clk, reset, PipeClearDE, PipeEnableDE, FRD2D, FRD2E);
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flopenrc #(64) DEReg3(clk, reset, PipeClearDE, PipeEnableDE, FRD3D, FRD3E);
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//*****************
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//other D/E pipe registers
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// other D/E pipe registers
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//*****************
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flopenrc #(1) DEReg4(clk, reset, PipeClearDE, PipeEnableDE, FWriteEnD, FWriteEnE);
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flopenrc #(3) DEReg5(clk, reset, PipeClearDE, PipeEnableDE, FResultSelD, FResultSelE);
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@ -250,22 +223,8 @@ module fpu (
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flopenrc #(1) DEReg16(clk, reset, PipeClearDE, PipeEnableDE, FOutputInput2D, FOutputInput2E);
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flopenrc #(2) DEReg17(clk, reset, PipeClearDE, PipeEnableDE, FMemRWD, FMemRWE);
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//EXECUTION STAGE
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// input muxs for forwarding
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mux4 #(64) FInput1Emux(FRD1E, FPUResult64W, FPUResult64E, SrcAM, FForwardInput1E, FInput1tmpE);
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mux3 #(64) FInput2Emux(FRD2E, FPUResult64W, FPUResult64E, FForwardInput2E, FInput2E);
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@ -274,7 +233,7 @@ module fpu (
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fma1 fma1 (.*);
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//first and only instance of floating-point divider
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// first and only instance of floating-point divider
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logic fpdivClk;
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clockgater fpdivclkg(.E(FDivStartE),
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@ -284,33 +243,18 @@ module fpu (
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fpdiv fpdivsqrt (.DivOpType(FOpCtrlE[0]), .clk(fpdivClk));
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//first of two-stage instance of floating-point add/cvt unit
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// first of two-stage instance of floating-point add/cvt unit
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fpuaddcvt1 fpadd1 (.*);
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//first of two-stage instance of floating-point comparator
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// first of two-stage instance of floating-point comparator
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fpucmp1 fpcmp1 (WE, XE, ANaNE, BNaNE, AzeroE, BzeroE, FInput1E, FInput2E, FOpCtrlE[1:0]);
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//first and only instance of floating-point sign converter
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// first and only instance of floating-point sign converter
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fpusgn fpsgn (.SgnOpCodeE(FOpCtrlE[1:0]),.*);
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//first and only instance of floating-point classify unit
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// first and only instance of floating-point classify unit
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fpuclassify fpuclass (.*);
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//*****************
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//fpregfile D/E pipe registers
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//*****************
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@ -319,7 +263,7 @@ module fpu (
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flopenrc #(64) EMFpReg3(clk, reset, PipeClearEM, PipeEnableEM, FInput3E, FInput3M);
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//*****************
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//fma E/M pipe registers
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// fma E/M pipe registers
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//*****************
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flopenrc #(13) EMRegFma1(clk, reset, PipeClearEM, PipeEnableEM, aligncntE, aligncntM);
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flopenrc #(106) EMRegFma2(clk, reset, PipeClearEM, PipeEnableEM, rE, rM);
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@ -348,7 +292,7 @@ module fpu (
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flopenrc #(1) EMRegFma25(clk, reset, PipeClearEM, PipeEnableEM, prodinfE, prodinfM);
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//*****************
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//fpadd E/M pipe registers
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// fpadd E/M pipe registers
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//*****************
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flopenrc #(64) EMRegAdd1(clk, reset, PipeClearEM, PipeEnableEM, AddSumE, AddSumM);
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flopenrc #(64) EMRegAdd2(clk, reset, PipeClearEM, PipeEnableEM, AddSumTcE, AddSumTcM);
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@ -377,7 +321,7 @@ module fpu (
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flopenrc #(1) EMRegAdd27(clk, reset, PipeClearEM, PipeEnableEM, AddUnEnE, AddUnEnM);
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//*****************
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//fpcmp E/M pipe registers
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// fpcmp E/M pipe registers
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//*****************
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flopenrc #(8) EMRegCmp1(clk, reset, PipeClearEM, PipeEnableEM, WE, WM);
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flopenrc #(8) EMRegCmp2(clk, reset, PipeClearEM, PipeEnableEM, XE, XM);
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@ -386,15 +330,15 @@ module fpu (
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flopenrc #(1) EMRegCmp5(clk, reset, PipeClearEM, PipeEnableEM, AzeroE, AzeroM);
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flopenrc #(1) EMRegCmp6(clk, reset, PipeClearEM, PipeEnableEM, BzeroE, BzeroM);
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//put this in for the event we want to delay fsgn - will otherwise bypass
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// put this in for the event we want to delay fsgn - will otherwise bypass
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//*****************
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//fpsgn E/M pipe registers
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// fpsgn E/M pipe registers
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//*****************
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flopenrc #(64) EMRegSgn2(clk, reset, PipeClearEM, PipeEnableEM, SgnResultE, SgnResultM);
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flopenrc #(5) EMRegSgn3(clk, reset, PipeClearEM, PipeEnableEM, SgnFlagsE, SgnFlagsM);
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//*****************
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//other E/M pipe registers
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// other E/M pipe registers
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//*****************
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flopenrc #(1) EMReg1(clk, reset, PipeClearEM, PipeEnableEM, FWriteEnE, FWriteEnM);
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flopenrc #(3) EMReg2(clk, reset, PipeClearEM, PipeEnableEM, FResultSelE, FResultSelM);
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@ -406,17 +350,10 @@ module fpu (
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flopenrc #(2) EMReg8(clk, reset, PipeClearEM, PipeEnableEM, FMemRWE, FMemRWM);
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//*****************
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//fpuclassify E/M pipe registers
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// fpuclassify E/M pipe registers
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//*****************
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flopenrc #(64) EMRegClass(clk, reset, PipeClearEM, PipeEnableEM, ClassResultE, ClassResultM);
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//BEGIN MEMORY STAGE
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assign FWriteDataM = FInput1M;
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@ -425,56 +362,47 @@ module fpu (
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fma2 fma2(.*);
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//second instance of two-stage floating-point add/cvt unit
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// second instance of two-stage floating-point add/cvt unit
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fpuaddcvt2 fpadd2 (.*);
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//second instance of two-stage floating-point comparator
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fpucmp2 fpcmp2 (.Invalid(CmpInvalidM), .FCC(CmpFCCM), .ANaN(ANaNM), .BNaN(BNaNM), .Azero(AzeroM), .Bzero(BzeroM), .w(WM), .x(XM), .Sel({1'b0, FmtM}), .op1(FInput1M), .op2(FInput2M), .*);
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// second instance of two-stage floating-point comparator
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fpucmp2 fpcmp2 (.Invalid(CmpInvalidM), .FCC(CmpFCCM), .ANaN(ANaNM), .BNaN(BNaNM), .Azero(AzeroM),
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.Bzero(BzeroM), .w(WM), .x(XM), .Sel({1'b0, FmtM}), .op1(FInput1M), .op2(FInput2M), .*);
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//*****************
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//fma M/W pipe registers
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// fma M/W pipe registers
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//*****************
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flopenrc #(64) MWRegFma1(clk, reset, PipeClearMW, PipeEnableMW, FmaResultM, FmaResultW);
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flopenrc #(5) MWRegFma2(clk, reset, PipeClearMW, PipeEnableMW, FmaFlagsM, FmaFlagsW);
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//*****************
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//fpdiv M/W pipe registers
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// fpdiv M/W pipe registers
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//*****************
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flopenrc #(64) MWRegDiv1(clk, reset, PipeClearMW, PipeEnableMW, FDivResultM, FDivResultW);
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flopenrc #(5) MWRegDiv2(clk, reset, PipeClearMW, PipeEnableMW, FDivFlagsM, FDivFlagsW);
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flopenrc #(1) MWRegDiv3(clk, reset, PipeClearMW, PipeEnableMW, DivDenormM, DivDenormW);
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//*****************
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//fpadd M/W pipe registers
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// fpadd M/W pipe registers
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//*****************
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flopenrc #(64) MWRegAdd1(clk, reset, PipeClearMW, PipeEnableMW, FAddResultM, FAddResultW);
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flopenrc #(5) MWRegAdd2(clk, reset, PipeClearMW, PipeEnableMW, FAddFlagsM, FAddFlagsW);
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//*****************
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//fpcmp M/W pipe registers
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// fpcmp M/W pipe registers
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//*****************
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flopenrc #(1) MWRegCmp1(clk, reset, PipeClearMW, PipeEnableMW, CmpInvalidM, CmpInvalidW);
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flopenrc #(2) MWRegCmp2(clk, reset, PipeClearMW, PipeEnableMW, CmpFCCM, CmpFCCW);
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flopenrc #(64) MWRegCmp3(clk, reset, PipeClearMW, PipeEnableMW, FCmpResultM, FCmpResultW);
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//*****************
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//fpsgn M/W pipe registers
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// fpsgn M/W pipe registers
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//*****************
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flopenrc #(64) MWRegSgn1(clk, reset, PipeClearMW, PipeEnableMW, SgnResultM, SgnResultW);
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flopenrc #(5) MWRegSgn2(clk, reset, PipeClearMW, PipeEnableMW, SgnFlagsM, SgnFlagsW);
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//*****************
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//other M/W pipe registers
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// other M/W pipe registers
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//*****************
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flopenrc #(1) MWReg1(clk, reset, PipeClearMW, PipeEnableMW, FWriteEnM, FWriteEnW);
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flopenrc #(3) MWReg2(clk, reset, PipeClearMW, PipeEnableMW, FResultSelM, FResultSelW);
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@ -484,21 +412,13 @@ module fpu (
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flopenrc #(64) MWReg6(clk, reset, PipeClearMW, PipeEnableMW, FLoadStoreResultM, FLoadStoreResultW);
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flopenrc #(1) MWReg7(clk, reset, PipeClearMW, PipeEnableMW, FWriteIntM, FWriteIntW);
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//*****************
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//fpuclassify M/W pipe registers
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// fpuclassify M/W pipe registers
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//*****************
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flopenrc #(64) MWRegClass(clk, reset, PipeClearMW, PipeEnableMW, ClassResultM, ClassResultW);
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//#########################################
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//BEGIN WRITEBACK STAGE
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// BEGIN WRITEBACK STAGE
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//#########################################
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always_comb begin
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@ -523,7 +443,6 @@ module fpu (
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endcase
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end
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always_comb begin
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case (FResultSelW)
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// div/sqrt
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@ -544,16 +463,17 @@ module fpu (
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3'b111 : FPUResult64W = FLoadStoreResultW;
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default : FPUResult64W = {64{1'bx}};
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endcase
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end
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//interface between XLEN size datapath and double-precision sized
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//floating-point results
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//
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//define offsets for LSB zero extension or truncation
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always_comb begin
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end // always_comb
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//zero extension
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// interface between XLEN size datapath and double-precision sized
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// floating-point results
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//
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// define offsets for LSB zero extension or truncation
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always_comb begin
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// zero extension
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FPUResultW = FPUResult64W[63:64-`XLEN];
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SetFflagsM = FPUFlagsW;
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end
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endmodule
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endmodule // fpu
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@ -76,7 +76,7 @@ module muldiv (
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assign Den0 = W64E ? {{32{SrcBE[31]&signedDivide}}, SrcBE[31:0]} : SrcBE;
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end else begin // RV32 has no W-type instructions
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assign Num0 = SrcAE;
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assign Den0 = SrcAE;
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assign Den0 = SrcBE;
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end
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// capture the Numerator/Denominator
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@ -320,11 +320,11 @@ string tests32f[] = '{
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"rv32m/I-MUL-01", "2000",
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"rv32m/I-MULH-01", "2000",
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"rv32m/I-MULHSU-01", "2000",
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"rv32m/I-MULHU-01", "2000"
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//"rv32m/I-DIV-01", "2000",
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//"rv32m/I-DIVU-01", "2000",
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//"rv32m/I-REM-01", "2000",
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//"rv32m/I-REMU-01", "2000"
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"rv32m/I-MULHU-01", "2000",
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"rv32m/I-DIV-01", "2000",
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"rv32m/I-DIVU-01", "2000",
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"rv32m/I-REM-01", "2000",
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"rv32m/I-REMU-01", "2000"
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};
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string tests32ic[] = '{
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