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https://github.com/openhwgroup/cvw
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Change busybear testbench to reflect new location of InstrF
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parent
e32291bcc2
commit
bab0e3b90f
@ -46,7 +46,7 @@ add wave -divider
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add wave -hex /testbench_busybear/PCtext
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add wave -hex /testbench_busybear/PCtext
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add wave -hex /testbench_busybear/pcExpected
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add wave -hex /testbench_busybear/pcExpected
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add wave -hex /testbench_busybear/dut/hart/ifu/PCF
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add wave -hex /testbench_busybear/dut/hart/ifu/PCF
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add wave -hex /testbench_busybear/dut/hart/ifu/InstrF
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add wave -hex /testbench_busybear/dut/hart/ifu/ic/InstrF
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add wave -hex /testbench_busybear/dut/hart/ifu/StallD
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add wave -hex /testbench_busybear/dut/hart/ifu/StallD
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add wave -hex /testbench_busybear/dut/hart/ifu/FlushD
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add wave -hex /testbench_busybear/dut/hart/ifu/FlushD
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add wave -hex /testbench_busybear/dut/hart/ifu/InstrRawD
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add wave -hex /testbench_busybear/dut/hart/ifu/InstrRawD
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@ -356,10 +356,10 @@ module testbench_busybear();
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logic [31:0] InstrMask;
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logic [31:0] InstrMask;
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logic forcedInstr;
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logic forcedInstr;
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logic [63:0] lastPCF;
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logic [63:0] lastPCF;
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always @(dut.PCF or dut.hart.ifu.InstrF or reset) begin
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always @(dut.PCF or dut.hart.ifu.ic.InstrF or reset) begin
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if(~HWRITE) begin
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if(~HWRITE) begin
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#3;
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#3;
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if (~reset && dut.hart.ifu.InstrF[15:0] !== {16{1'bx}} && ~dut.hart.StallD) begin
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if (~reset && dut.hart.ifu.ic.InstrF[15:0] !== {16{1'bx}} && ~dut.hart.StallD) begin
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if (dut.PCF !== lastPCF) begin
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if (dut.PCF !== lastPCF) begin
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lastCheckInstrF = CheckInstrF;
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lastCheckInstrF = CheckInstrF;
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lastPC <= dut.PCF;
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lastPC <= dut.PCF;
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@ -367,23 +367,23 @@ module testbench_busybear();
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if (speculative && (lastPC != pcExpected)) begin
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if (speculative && (lastPC != pcExpected)) begin
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speculative = ~equal(dut.PCF,pcExpected,3);
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speculative = ~equal(dut.PCF,pcExpected,3);
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if(dut.PCF===pcExpected) begin
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if(dut.PCF===pcExpected) begin
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if(dut.hart.ifu.InstrF[6:0] == 7'b1010011) begin // for now, NOP out any float instrs
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if(dut.hart.ifu.ic.InstrF[6:0] == 7'b1010011) begin // for now, NOP out any float instrs
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force CheckInstrF = 32'b0010011;
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force CheckInstrF = 32'b0010011;
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release CheckInstrF;
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release CheckInstrF;
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force dut.hart.ifu.InstrF = 32'b0010011;
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force dut.hart.ifu.ic.InstrF = 32'b0010011;
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#7;
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#7;
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release dut.hart.ifu.InstrF;
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release dut.hart.ifu.ic.InstrF;
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$display("warning: NOPing out %s at PC=%0x, instr %0d, time %0t", PCtext, dut.PCF, instrs, $time);
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$display("warning: NOPing out %s at PC=%0x, instr %0d, time %0t", PCtext, dut.PCF, instrs, $time);
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warningCount += 1;
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warningCount += 1;
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forcedInstr = 1;
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forcedInstr = 1;
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end
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end
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else begin
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else begin
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if(dut.hart.ifu.InstrF[28:27] != 2'b11 && dut.hart.ifu.InstrF[6:0] == 7'b0101111) begin //for now, replace non-SC A instrs with LD
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if(dut.hart.ifu.ic.InstrF[28:27] != 2'b11 && dut.hart.ifu.ic.InstrF[6:0] == 7'b0101111) begin //for now, replace non-SC A instrs with LD
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force CheckInstrF = {12'b0, CheckInstrF[19:7], 7'b0000011};
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force CheckInstrF = {12'b0, CheckInstrF[19:7], 7'b0000011};
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release CheckInstrF;
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release CheckInstrF;
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force dut.hart.ifu.InstrF = {12'b0, dut.hart.ifu.InstrF[19:7], 7'b0000011};
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force dut.hart.ifu.ic.InstrF = {12'b0, dut.hart.ifu.ic.InstrF[19:7], 7'b0000011};
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#7;
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#7;
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release dut.hart.ifu.InstrF;
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release dut.hart.ifu.ic.InstrF;
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$display("warning: replacing AMO instr %s at PC=%0x with ld", PCtext, dut.PCF);
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$display("warning: replacing AMO instr %s at PC=%0x with ld", PCtext, dut.PCF);
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warningCount += 1;
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warningCount += 1;
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forcedInstr = 1;
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forcedInstr = 1;
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@ -406,23 +406,23 @@ module testbench_busybear();
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end
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end
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scan_file_PC = $fscanf(data_file_PC, "%x\n", CheckInstrF);
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scan_file_PC = $fscanf(data_file_PC, "%x\n", CheckInstrF);
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if(dut.PCF === pcExpected) begin
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if(dut.PCF === pcExpected) begin
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if(dut.hart.ifu.InstrF[6:0] == 7'b1010011) begin // for now, NOP out any float instrs
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if(dut.hart.ifu.ic.InstrF[6:0] == 7'b1010011) begin // for now, NOP out any float instrs
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force CheckInstrF = 32'b0010011;
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force CheckInstrF = 32'b0010011;
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release CheckInstrF;
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release CheckInstrF;
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force dut.hart.ifu.InstrF = 32'b0010011;
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force dut.hart.ifu.ic.InstrF = 32'b0010011;
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#7;
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#7;
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release dut.hart.ifu.InstrF;
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release dut.hart.ifu.ic.InstrF;
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$display("warning: NOPing out %s at PC=%0x, instr %0d, time %0t", PCtext, dut.PCF, instrs, $time);
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$display("warning: NOPing out %s at PC=%0x, instr %0d, time %0t", PCtext, dut.PCF, instrs, $time);
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warningCount += 1;
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warningCount += 1;
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forcedInstr = 1;
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forcedInstr = 1;
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end
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end
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else begin
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else begin
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if(dut.hart.ifu.InstrF[28:27] != 2'b11 && dut.hart.ifu.InstrF[6:0] == 7'b0101111) begin //for now, replace non-SC A instrs with LD
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if(dut.hart.ifu.ic.InstrF[28:27] != 2'b11 && dut.hart.ifu.ic.InstrF[6:0] == 7'b0101111) begin //for now, replace non-SC A instrs with LD
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force CheckInstrF = {12'b0, CheckInstrF[19:7], 7'b0000011};
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force CheckInstrF = {12'b0, CheckInstrF[19:7], 7'b0000011};
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release CheckInstrF;
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release CheckInstrF;
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force dut.hart.ifu.InstrF = {12'b0, dut.hart.ifu.InstrF[19:7], 7'b0000011};
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force dut.hart.ifu.ic.InstrF = {12'b0, dut.hart.ifu.ic.InstrF[19:7], 7'b0000011};
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#7;
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#7;
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release dut.hart.ifu.InstrF;
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release dut.hart.ifu.ic.InstrF;
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$display("warning: replacing AMO instr %s at PC=%0x with ld", PCtext, dut.PCF);
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$display("warning: replacing AMO instr %s at PC=%0x with ld", PCtext, dut.PCF);
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warningCount += 1;
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warningCount += 1;
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forcedInstr = 1;
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forcedInstr = 1;
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@ -467,8 +467,8 @@ module testbench_busybear();
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`ERROR
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`ERROR
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end
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end
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InstrMask = CheckInstrF[1:0] == 2'b11 ? 32'hFFFFFFFF : 32'h0000FFFF;
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InstrMask = CheckInstrF[1:0] == 2'b11 ? 32'hFFFFFFFF : 32'h0000FFFF;
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if ((~forcedInstr) && (~speculative) && ((InstrMask & dut.hart.ifu.InstrF) !== (InstrMask & CheckInstrF))) begin
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if ((~forcedInstr) && (~speculative) && ((InstrMask & dut.hart.ifu.ic.InstrF) !== (InstrMask & CheckInstrF))) begin
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$display("%0t ps, instr %0d: InstrF does not equal CheckInstrF: %x, %x, PC: %x", $time, instrs, dut.hart.ifu.InstrF, CheckInstrF, dut.PCF);
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$display("%0t ps, instr %0d: InstrF does not equal CheckInstrF: %x, %x, PC: %x", $time, instrs, dut.hart.ifu.ic.InstrF, CheckInstrF, dut.PCF);
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`ERROR
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`ERROR
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end
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end
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end
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end
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@ -481,7 +481,7 @@ module testbench_busybear();
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// Track names of instructions
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// Track names of instructions
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string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
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string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
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logic [31:0] InstrW;
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logic [31:0] InstrW;
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instrNameDecTB dec(dut.hart.ifu.InstrF, InstrFName);
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instrNameDecTB dec(dut.hart.ifu.ic.InstrF, InstrFName);
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instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
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instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
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dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
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dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
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dut.hart.ifu.InstrM, InstrW,
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dut.hart.ifu.InstrM, InstrW,
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