From 1deb44b0fcc35cc8e9bca247d0d8b5a8ff58bbb7 Mon Sep 17 00:00:00 2001 From: James Stine Date: Tue, 4 Jun 2024 10:56:44 -0500 Subject: [PATCH 1/4] fix operator for tap.sv --- src/debug/tap.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/debug/tap.sv b/src/debug/tap.sv index ab7f46a93..74ec6ad8e 100644 --- a/src/debug/tap.sv +++ b/src/debug/tap.sv @@ -90,8 +90,8 @@ module tap ( updateDR <= State == UpdateDR; end - assign clockIR = tck || State[0] || ~State[1] || ~State[3]; - assign clockDR = tck || State[0] || ~State[1] || State[3]; + assign clockIR = tck | State[0] | ~State[1] | ~State[3]; + assign clockDR = tck | State[0] | ~State[1] | State[3]; assign select = State[3]; endmodule From bdbd310bb4f88bef7a99f8b9741dd800c3c98743 Mon Sep 17 00:00:00 2001 From: James Stine Date: Tue, 4 Jun 2024 10:57:56 -0500 Subject: [PATCH 2/4] fix operator for dm.sv --- src/debug/dm.sv | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/src/debug/dm.sv b/src/debug/dm.sv index a39bf4512..db839b6cf 100644 --- a/src/debug/dm.sv +++ b/src/debug/dm.sv @@ -77,7 +77,7 @@ module dm import cvw::*; #(parameter cvw_t P) ( logic HaltOnReset; logic Halted; - hartcontrol hartcontrol(.clk, .rst(rst || ~DmActive), .NdmReset, .HaltReq, + hartcontrol hartcontrol(.clk, .rst(rst | ~DmActive), .NdmReset, .HaltReq, .ResumeReq, .HaltOnReset, .DebugStall, .Halted, .AllRunning, .AnyRunning, .AllHalted, .AnyHalted, .AllResumeAck, .AnyResumeAck); @@ -184,7 +184,7 @@ module dm import cvw::*; #(parameter cvw_t P) ( ConfStrPtrValid <= 0; CmdErr <= 0; if (ReqValid) begin - if (ReqAddress == `DMCONTROL && ReqOP == `OP_WRITE && ReqData[`DMACTIVE]) begin + if (ReqAddress == `DMCONTROL & ReqOP == `OP_WRITE & ReqData[`DMACTIVE]) begin DmActive <= ReqData[`DMACTIVE]; RspOP <= `OP_SUCCESS; end @@ -247,7 +247,7 @@ module dm import cvw::*; #(parameter cvw_t P) ( W_DMCONTROL : begin // While an abstract command is executing (busy in abstractcs is high), a debugger must not change // hartsel, and must not write 1 to haltreq, resumereq, ackhavereset, setresethaltreq, or clrresethaltreq - if (Busy && (ReqData[`HALTREQ] || ReqData[`RESUMEREQ] || ReqData[`SETRESETHALTREQ] || ReqData[`CLRRESETHALTREQ])) + if (Busy & (ReqData[`HALTREQ] | ReqData[`RESUMEREQ] | ReqData[`SETRESETHALTREQ] | ReqData[`CLRRESETHALTREQ])) CmdErr <= ~|CmdErr ? `CMDERR_BUSY : CmdErr; else begin HaltReq <= ReqData[`HALTREQ]; @@ -316,7 +316,7 @@ module dm import cvw::*; #(parameter cvw_t P) ( else if (~ReqData[`TRANSFER]); // If not TRANSFER, do nothing else if (InvalidRegNo) CmdErr <= `CMDERR_EXCEPTION; // If InvalidRegNo, set CmdErr, do nothing - else if (ReqData[`AARWRITE] && RegReadOnly) + else if (ReqData[`AARWRITE] & RegReadOnly) CmdErr <= `CMDERR_NOT_SUPPORTED; // If writing to a read only register, set CmdErr, do nothing else begin AcWrite <= ReqData[`AARWRITE]; @@ -374,7 +374,7 @@ module dm import cvw::*; #(parameter cvw_t P) ( AC_SCAN : begin if (Cycle == ScanChainLen) - AcState <= (GPRRegNo && AcWrite) ? AC_GPRUPDATE : AC_IDLE; + AcState <= (GPRRegNo & AcWrite) ? AC_GPRUPDATE : AC_IDLE; else Cycle <= Cycle + 1; end @@ -391,12 +391,12 @@ module dm import cvw::*; #(parameter cvw_t P) ( assign DebugGPRUpdate = (AcState == AC_GPRUPDATE); // Scan Chain - assign GPRSel = GPRRegNo && (AcState != AC_IDLE); + assign GPRSel = GPRRegNo & (AcState != AC_IDLE); assign ScanReg[P.XLEN] = GPRSel ? GPRScanIn : ScanIn; assign ScanOut = GPRSel ? 1'b0 : ScanReg[0]; assign GPRScanOut = GPRSel ? ScanReg[0] : 1'b0; - assign ScanEn = ~GPRSel && (AcState == AC_SCAN); - assign GPRScanEn = GPRSel && (AcState == AC_SCAN); + assign ScanEn = ~GPRSel & (AcState == AC_SCAN); + assign GPRScanEn = GPRSel & (AcState == AC_SCAN); // Load data from message registers into scan chain if (P.XLEN == 32) @@ -406,30 +406,30 @@ module dm import cvw::*; #(parameter cvw_t P) ( else if (P.XLEN == 128) assign PackedDataReg = {Data3,Data2,Data1,Data0}; - assign WriteScanReg = AcWrite && (~GPRRegNo && (Cycle == ShiftCount) || GPRRegNo && (Cycle == 0)); + assign WriteScanReg = AcWrite & (~GPRRegNo & (Cycle == ShiftCount) | GPRRegNo & (Cycle == 0)); genvar i; for (i=0; i= 64) begin assign Data1Wr = StoreScanChain ? MaskedScanReg[63:32] : ReqData; - flopenr #(32) data1reg (.clk, .reset(rst), .en(StoreScanChain || WriteMsgReg && (ReqAddress == `DATA1)), .d(Data1Wr), .q(Data1)); + flopenr #(32) data1reg (.clk, .reset(rst), .en(StoreScanChain | WriteMsgReg & (ReqAddress == `DATA1)), .d(Data1Wr), .q(Data1)); end if (P.XLEN == 128) begin assign Data2Wr = StoreScanChain ? MaskedScanReg[95:64] : ReqData; assign Data3Wr = StoreScanChain ? MaskedScanReg[127:96] : ReqData; - flopenr #(32) data2reg (.clk, .reset(rst), .en(StoreScanChain || WriteMsgReg && (ReqAddress == `DATA2)), .d(Data2Wr), .q(Data2)); - flopenr #(32) data3reg (.clk, .reset(rst), .en(StoreScanChain || WriteMsgReg && (ReqAddress == `DATA3)), .d(Data3Wr), .q(Data3)); + flopenr #(32) data2reg (.clk, .reset(rst), .en(StoreScanChain | WriteMsgReg & (ReqAddress == `DATA2)), .d(Data2Wr), .q(Data2)); + flopenr #(32) data3reg (.clk, .reset(rst), .en(StoreScanChain | WriteMsgReg & (ReqAddress == `DATA3)), .d(Data3Wr), .q(Data3)); end rad #(P) regnodecode(.AarSize(ReqData[`AARSIZE]),.Regno(ReqData[`REGNO]),.GPRRegNo,.ScanChainLen,.ShiftCount,.InvalidRegNo,.RegReadOnly,.GPRAddr,.ARMask); From ae4900698ebb11e12eb9a5e004b43b778c023a34 Mon Sep 17 00:00:00 2001 From: James Stine Date: Tue, 4 Jun 2024 10:59:04 -0500 Subject: [PATCH 3/4] fix operator for ir and rad --- src/debug/ir.sv | 4 ++-- src/debug/rad.sv | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/debug/ir.sv b/src/debug/ir.sv index 767430884..dd99c7cc1 100644 --- a/src/debug/ir.sv +++ b/src/debug/ir.sv @@ -49,12 +49,12 @@ module ir ( // Shift register always @(posedge clockIR) begin - shift_reg[0] <= shift_reg[1] || captureIR; + shift_reg[0] <= shift_reg[1] | captureIR; end genvar i; for (i = INST_REG_WIDTH; i > 1; i = i - 1) begin always @(posedge clockIR) begin - shift_reg[i-1] <= shift_reg[i] && ~captureIR; + shift_reg[i-1] <= shift_reg[i] & ~captureIR; end end diff --git a/src/debug/rad.sv b/src/debug/rad.sv index 565316ea1..a1e8ec148 100644 --- a/src/debug/rad.sv +++ b/src/debug/rad.sv @@ -135,8 +135,8 @@ module rad import cvw::*; #(parameter cvw_t P) ( assign ARMask[31:0] = Mask[31:0]; if (P.XLEN >= 64) - assign ARMask[63:32] = (AarSize == 3'b011 || AarSize == 3'b100) ? Mask[63:32] : '0; + assign ARMask[63:32] = (AarSize == 3'b011 | AarSize == 3'b100) ? Mask[63:32] : '0; if (P.XLEN == 128) assign ARMask[127:64] = (AarSize == 3'b100) ? Mask[127:64] : '0; -endmodule \ No newline at end of file +endmodule From 345c8ce08d0bb9a55b47f5a780a2cbfc5bd52b52 Mon Sep 17 00:00:00 2001 From: James Stine Date: Tue, 4 Jun 2024 11:23:14 -0500 Subject: [PATCH 4/4] temporary assignment of JTAG ID --- src/debug/dm.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/debug/dm.sv b/src/debug/dm.sv index db839b6cf..38f31d263 100644 --- a/src/debug/dm.sv +++ b/src/debug/dm.sv @@ -65,7 +65,8 @@ module dm import cvw::*; #(parameter cvw_t P) ( logic [31:0] RspData; logic [1:0] RspOP; - localparam JTAG_DEVICE_ID = 32'hdeadbeef; // TODO: put JTAG device ID in parameter struct + // JTAG ID: [31:27] ver [27:12] part number [11:1] JEDEC number [0] set to 1 + localparam JTAG_DEVICE_ID = 32'h1000_1005; dtm #(`ADDR_WIDTH, JTAG_DEVICE_ID) dtm (.clk, .tck, .tdi, .tms, .tdo, .ReqReady, .ReqValid, .ReqAddress, .ReqData, .ReqOP, .RspReady,