From ba9320d82201916c77a6ae7aeda21786dd0ad78a Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Wed, 9 Mar 2022 13:58:17 +0000
Subject: [PATCH] Updated testbench to read expected flags

---
 pipelined/src/fma/fma16_testgen.c |  7 +++++--
 pipelined/src/fma/testbench.v     | 22 ++++++++++++----------
 2 files changed, 17 insertions(+), 12 deletions(-)

diff --git a/pipelined/src/fma/fma16_testgen.c b/pipelined/src/fma/fma16_testgen.c
index a9a26d803..f63f59106 100644
--- a/pipelined/src/fma/fma16_testgen.c
+++ b/pipelined/src/fma/fma16_testgen.c
@@ -37,7 +37,7 @@ float convFloat(float16_t f16) {
 
 void genCase(FILE *fptr, float16_t x, float16_t y, float16_t z, int mul, int add, int negp, int negz, int zeroAllowed, int infAllowed, int nanAllowed) {
     float16_t result;
-    int op;
+    int op, flagVals;
     char calc[80], flags[80];
     float32_t x32, y32, z32, r32;
     float xf, yf, zf, rf;
@@ -56,6 +56,9 @@ void genCase(FILE *fptr, float16_t x, float16_t y, float16_t z, int mul, int add
         (softfloat_exceptionFlags >> 2) % 2,
         (softfloat_exceptionFlags >> 1) % 2,
         (softfloat_exceptionFlags) % 2);
+    // pack these four flags into one nibble, discarding DZ flag
+    flagVals = softfloat_exceptionFlags & 0x7 | ((softfloat_exceptionFlags >> 1) & 0x8);
+
 
     // convert to floats for printing
     xf = convFloat(x);
@@ -75,7 +78,7 @@ void genCase(FILE *fptr, float16_t x, float16_t y, float16_t z, int mul, int add
     if (resultmag.v == 0x0000 && !zeroAllowed) fprintf(fptr, "// skip zero: ");
     if ((resultmag.v == 0x7C00 || resultmag.v == 0x7BFF) && !infAllowed)  fprintf(fptr, "// Skip inf: ");
     if (resultmag.v >  0x7C00 && !nanAllowed)  fprintf(fptr, "// Skip NaN: ");
-    fprintf(fptr, "%04x_%04x_%04x_%02x_%04x_%02x // %s %s\n", x.v, y.v, z.v, op, result.v, softfloat_exceptionFlags, calc, flags);
+    fprintf(fptr, "%04x_%04x_%04x_%02x_%04x_%01x // %s %s\n", x.v, y.v, z.v, op, result.v, flagVals, calc, flags);
 }
 
 void prepTests(uint16_t *e, uint16_t *f, char *testName, char *desc, float16_t *cases, 
diff --git a/pipelined/src/fma/testbench.v b/pipelined/src/fma/testbench.v
index 2767c4899..bef7eca41 100644
--- a/pipelined/src/fma/testbench.v
+++ b/pipelined/src/fma/testbench.v
@@ -1,12 +1,14 @@
 /* verilator lint_off STMTDLY */
 module testbench_fma16;
-  logic        clk, reset;
-  logic [15:0] x, y, z, rexpected, result;
-  logic [7:0]  ctrl;
-  logic        mul, add, negp, negz;
-  logic [1:0]  roundmode;
-  logic [31:0] vectornum, errors;
-  logic [71:0] testvectors[10000:0];
+  reg        clk, reset;
+  reg [15:0] x, y, z, rexpected;
+  wire [15:0] result;
+  reg [7:0]  ctrl;
+  reg [3:0]  flagsexpected;
+  reg        mul, add, negp, negz;
+  reg [1:0]  roundmode;
+  reg [31:0] vectornum, errors;
+  reg [75:0] testvectors[10000:0];
 
   // instantiate device under test
   fma16 dut(x, y, z, mul, add, negp, negz, roundmode, result);
@@ -20,7 +22,7 @@ module testbench_fma16;
   // at start of test, load vectors and pulse reset
   initial
     begin
-      $readmemh("work/fmul_2.tv", testvectors);
+      $readmemh("work/fmul_0.tv", testvectors);
       vectornum = 0; errors = 0;
       reset = 1; #22; reset = 0;
     end
@@ -28,14 +30,14 @@ module testbench_fma16;
   // apply test vectors on rising edge of clk
   always @(posedge clk)
     begin
-      #1; {x, y, z, ctrl, rexpected} = testvectors[vectornum];
+      #1; {x, y, z, ctrl, rexpected, flagsexpected} = testvectors[vectornum];
       {roundmode, mul, add, negp, negz} = ctrl[5:0];
     end
 
   // check results on falling edge of clk
   always @(negedge clk)
     if (~reset) begin // skip during reset
-      if (result !== rexpected) begin  // check result
+      if (result !== rexpected) begin  // check result     // *** should also add tests on flags eventually
         $display("Error: inputs %h * %h + %h", x, y, z);
         $display("  result = %h (%h expected)", result, rexpected);
         errors = errors + 1;