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	Merge pull request #85 from stineje/main
Fix bugs in scripts for synthesis and tsmc28 psyn
This commit is contained in:
		
						commit
						ba6eef1118
					
				@ -18,20 +18,22 @@ if {$tech == "sky130"} {
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    set s9lib $timing_lib/sky90/sky90_sc/V1.7.4/lib
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    lappend search_path $s9lib
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} elseif {$tech == "tsmc28"} {
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    set s10lib /proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a
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    set pdk /proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/
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    set s10lib $pdk/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a
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    lappend search_path $s10lib
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}
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elseif {$tech == "tsmc28psyn"} {
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    set TLU /home/jstine/TLU+
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    set s10lib /proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a
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    set pdk /proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/
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    set s10lib $pdk/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a
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    lappend search_path $s10lib
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    set TLUPLUS true
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    set mw_logic1_net VDD
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    set mw_logic0_net VSS
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    set TLU_PDK /import/yukari1/jstine/TLU+/
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    set TLU_PDK /home/jstine/TLU+/
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    set CAPTABLE $TLU/1p8m/
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    set MW_REFERENCE_LIBRARY /home/jstine/MW
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    set MW_TECH_FILE tcbn28hpcplusbwp7t30p140
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    set MW_TECH_FILE tcbn28hpcplusbwp30p140
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    set MAX_TLU_FILE $CAPTABLE/crn28hpc+_1p08m+ut-alrdl_5x1z1u_typical.tluplus
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    set MIN_TLU_FILE $CAPTABLE/crn28hpc+_1p08m+ut-alrdl_5x1z1u_rcworst.tluplus
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    set PRS_MAP_FILE $MW_REFERENCE_LIBRARY/astro_layername.map
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@ -50,11 +52,10 @@ if {$tech == "sky130"} {
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    lappend target_library $s9lib/scc9gena_tt_1.2v_25C.db
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} elseif {$tech == "tsmc28"} {
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    lappend target_library $s10lib/tcbn28hpcplusbwp30p140tt0p9v25c.db
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}
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} elseif {$tech == "tsmc28psyn"} {
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    set mw_reference_library [list ]    
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    lappend target_library $s10lib/tcbn28hpcplusbwp30p140tt0p9v25c.db
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    lappend mw_reference_library $MW_REFERENCE_LIBRARY/tcbn28hpcplusbwp7t30p140    
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    lappend mw_reference_library $MW_REFERENCE_LIBRARY/tcbn28hpcplusbwp30p140    
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}
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# Set Link Library
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@ -5,9 +5,9 @@ import subprocess
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from multiprocessing import Pool
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import argparse
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def runSynth(config, mod, tech, freq, maxopt, usesram):
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def runSynth(config, mod, tech, freq, maxopt, usesram, usetopo):
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    global pool
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    command = "make synth DESIGN=wallypipelinedcore CONFIG={} MOD={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} USESRAM={} MAXCORES=1".format(config, mod, tech, freq, maxopt, usesram)
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    command = "make synth DESIGN=wallypipelinedcore CONFIG={} MOD={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} USESRAM={} USETOPO={} MAXCORES=1".format(config, mod, tech, freq, maxopt, usesram, usetopo)
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    pool.map(mask, [command])
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def mask(command):
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@ -33,32 +33,34 @@ if __name__ == '__main__':
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    parser.add_argument("-e", "--tech", choices=techs, help = "Technology")
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    parser.add_argument("-o", "--maxopt", action='store_true', help = "Turn on MAXOPT")
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    parser.add_argument("-r", "--usesram", action='store_true', help = "Use SRAM modules")
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    parser.add_argument("-topo", "--usetopo", action='store_true', help = "Run physical synthesis")	
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    args = parser.parse_args()
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    tech = args.tech if args.tech else 'sky90'
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    maxopt = int(args.maxopt)
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    usesram = int(args.usesram)
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    usetopo = int(args.usetopop)	
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    mod = 'orig'
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    if args.freqsweep:
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        sc = args.freqsweep
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        config = args.version if args.version else 'rv32e'
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        for freq in [round(sc+sc*x/100) for x in freqVaryPct]: # rv32e freq sweep
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            runSynth(config, mod, tech, freq, maxopt, usesram)
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            runSynth(config, mod, tech, freq, maxopt, usesram, usetopo)
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    if args.configsweep:
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        defaultfreq = 1500 if tech == 'sky90' else 5000
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        freq = args.targetfreq if args.targetfreq else defaultfreq
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        for config in ['rv32i', 'rv64gc', 'rv64i', 'rv32gc', 'rv32imc', 'rv32e']: #configs
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            runSynth(config, mod, tech, freq, maxopt, usesram)
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            runSynth(config, mod, tech, freq, maxopt, usesram, usetopo)
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    if args.featuresweep:
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        defaultfreq = 500 if tech == 'sky90' else 1500
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        freq = args.targetfreq if args.targetfreq else defaultfreq
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        config = args.version if args.version else 'rv64gc'
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        for mod in ['noFPU', 'noMulDiv', 'noPriv', 'PMP0', 'orig']: 
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            runSynth(config, mod, tech, freq, maxopt, usesram)
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            runSynth(config, mod, tech, freq, maxopt, usesram, usetopo)
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    else:
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        defaultfreq = 500 if tech == 'sky90' else 1500
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        freq = args.targetfreq if args.targetfreq else defaultfreq
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        config = args.version if args.version else 'rv64gc'
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        runSynth(config, mod, tech, freq, maxopt, usesram)
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        runSynth(config, mod, tech, freq, maxopt, usesram, usetopo)
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