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Fixed possible bugs in LRSC.

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This commit is contained in:
Ross Thompson 2022-04-16 14:45:31 -05:00
parent 2e8afd071e
commit b9a19304db
4 changed files with 10 additions and 8 deletions
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4
pipelined/src/lsu/atomic.sv
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@ -32,7 +32,7 @@
module atomic ( module atomic (
input logic clk, input logic clk,
input logic reset, FlushW, CPUBusy, input logic reset, FlushW, StallW,
input logic [`XLEN-1:0] ReadDataM, input logic [`XLEN-1:0] ReadDataM,
input logic [`XLEN-1:0] LSUWriteDataM, input logic [`XLEN-1:0] LSUWriteDataM,
input logic [`PA_BITS-1:0] LSUPAdrM, input logic [`PA_BITS-1:0] LSUPAdrM,
@ -52,7 +52,7 @@ module atomic (
.result(AMOResult)); .result(AMOResult));
mux2 #(`XLEN) wdmux(LSUWriteDataM, AMOResult, LSUAtomicM[1], FinalAMOWriteDataM); mux2 #(`XLEN) wdmux(LSUWriteDataM, AMOResult, LSUAtomicM[1], FinalAMOWriteDataM);
assign MemReadM = PreLSURWM[1] & ~IgnoreRequest; assign MemReadM = PreLSURWM[1] & ~IgnoreRequest;
lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .PreLSURWM, .LSUAtomicM, .LSUPAdrM, lrsc lrsc(.clk, .reset, .FlushW, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .LSUPAdrM,
.SquashSCW, .LSURWM); .SquashSCW, .LSURWM);
endmodule endmodule

11
pipelined/src/lsu/lrsc.sv
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@ -34,7 +34,7 @@
module lrsc module lrsc
( (
input logic clk, reset, input logic clk, reset,
input logic FlushW, CPUBusy, input logic FlushW, StallW,
input logic MemReadM, input logic MemReadM,
input logic [1:0] PreLSURWM, input logic [1:0] PreLSURWM,
output logic [1:0] LSURWM, output logic [1:0] LSURWM,
@ -55,10 +55,11 @@ module lrsc
assign LSURWM = SquashSCM ? 2'b00 : PreLSURWM; assign LSURWM = SquashSCM ? 2'b00 : PreLSURWM;
always_comb begin // ReservationValidM (next value of valid reservation) always_comb begin // ReservationValidM (next value of valid reservation)
if (lrM) ReservationValidM = 1; // set valid on load reserve if (lrM) ReservationValidM = 1; // set valid on load reserve
else if (scM | WriteAdrMatchM) ReservationValidM = 0; // clear valid on store to same address or any sc // if we implement multiple harts invalidate reservation if another hart stores to this reservation.
else if (scM) ReservationValidM = 0; // clear valid on store to same address or any sc
else ReservationValidM = ReservationValidW; // otherwise don't change valid else ReservationValidM = ReservationValidW; // otherwise don't change valid
end end
flopenrc #(`PA_BITS-2) resadrreg(clk, reset, FlushW, lrM, LSUPAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid flopenr #(`PA_BITS-2) resadrreg(clk, reset, lrM & ~StallW, LSUPAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid
flopenrc #(1) resvldreg(clk, reset, FlushW, lrM, ReservationValidM, ReservationValidW); flopenr #(1) resvldreg(clk, reset, ~StallW, ReservationValidM, ReservationValidW);
flopenrc #(1) squashreg(clk, reset, FlushW, ~CPUBusy, SquashSCM, SquashSCW); flopenr #(1) squashreg(clk, reset, ~StallW, SquashSCM, SquashSCW);
endmodule endmodule

2
pipelined/src/lsu/lsu.sv
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@ -253,7 +253,7 @@ module lsu (
// Atomic operations // Atomic operations
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
if (`A_SUPPORTED) begin:atomic if (`A_SUPPORTED) begin:atomic
atomic atomic(.clk, .reset, .FlushW, .CPUBusy, .ReadDataM, .LSUWriteDataM, .LSUPAdrM, atomic atomic(.clk, .reset, .FlushW, .StallW, .ReadDataM, .LSUWriteDataM, .LSUPAdrM,
.LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest, .LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest,
.FinalAMOWriteDataM, .SquashSCW, .LSURWM); .FinalAMOWriteDataM, .SquashSCW, .LSURWM);
end else begin:lrsc end else begin:lrsc

1
pipelined/src/privileged/csrsr.sv
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@ -140,6 +140,7 @@ module csrsr (
STATUS_MIE <= #1 STATUS_MPIE; STATUS_MIE <= #1 STATUS_MPIE;
STATUS_MPIE <= #1 1; STATUS_MPIE <= #1 1;
STATUS_MPP <= #1 `U_SUPPORTED ? `U_MODE : `M_MODE; // per spec, not sure why STATUS_MPP <= #1 `U_SUPPORTED ? `U_MODE : `M_MODE; // per spec, not sure why
//STATUS_MPRV_INT <= #1 (STATUS_MPP == `M_MODE & STATUS_MPRV_INT); //0; // per 20210108 draft spec
STATUS_MPRV_INT <= #1 0; // per 20210108 draft spec STATUS_MPRV_INT <= #1 0; // per 20210108 draft spec
end else if (sretM) begin end else if (sretM) begin
STATUS_SIE <= #1 STATUS_SPIE; STATUS_SIE <= #1 STATUS_SPIE;