diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv
index 6c3ae803e..d6915666d 100644
--- a/wally-pipelined/src/cache/dcache.sv
+++ b/wally-pipelined/src/cache/dcache.sv
@@ -433,7 +433,14 @@ module dcache
     case (CurrState)
       STATE_READY: begin
 	// TLB Miss	
-	if(AnyCPUReqM & DTLBMissM) begin  
+	if(AnyCPUReqM & DTLBMissM) begin
+	  // the LSU arbiter has not yet selected the PTW.
+	  // The CPU needs to be stalled until that happens.
+	  // If we set DCacheStall for 1 cycle before going to
+	  // PTW ready the CPU will stall.
+	  // The page table walker asserts it's control 1 cycle
+	  // after the TLBs miss.
+	  DCacheStall = 1'b1;
 	  NextState = STATE_PTW_READY;
 	end
 	// amo hit
@@ -580,6 +587,7 @@ module dcache
       end
 
       STATE_PTW_READY: begin
+	// now all output connect to PTW instead of CPU.
 	CommittedM = 1'b1;
 	// return to ready if page table walk completed.
 	if(DTLBWriteM) begin
diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv
index 334ef2b26..5beddf487 100644
--- a/wally-pipelined/src/mmu/pagetablewalker.sv
+++ b/wally-pipelined/src/mmu/pagetablewalker.sv
@@ -77,7 +77,6 @@ module pagetablewalker
     if (`MEM_VIRTMEM) begin
       // Internal signals
       // register TLBs translation miss requests
-      logic [`XLEN-1:0] 	    TranslationVAdrQ;
       logic 			    ITLBMissFQ, DTLBMissMQ;
       
       logic [`PPN_BITS-1:0] 	    BasePageTablePPN;
@@ -138,13 +137,6 @@ module pagetablewalker
       assign TranslationVAdr = (SelDataTranslation) ? MemAdrM : PCF; // *** need to register TranslationVAdr
       assign SelDataTranslation = DTLBMissMQ | DTLBMissM;
 
-      flopenr #(`XLEN) 
-      TranslationVAdrReg(.clk(clk),
-			 .reset(reset),
-			 .en(StartWalk),
-			 .d(TranslationVAdr),
-			 .q(TranslationVAdrQ));
-
       flopenrc #(1)
       DTLBMissMReg(.clk(clk),
 		   .reset(reset),
@@ -170,7 +162,7 @@ module pagetablewalker
 		       (WalkerState == LEVEL3 && ValidPTE && LeafPTE && ~AccessAlert) ||		   
 		       (WalkerState == FAULT);
       
-      assign HPTWTranslate = (DTLBMissMQ | ITLBMissFQ) & ~EndWalk;
+      assign HPTWTranslate = (DTLBMissMQ | ITLBMissFQ);
       //assign HPTWTranslate = DTLBMissM | ITLBMissF;
 
       // unswizzle PTE bits
diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv
index b6a206023..418ddc424 100644
--- a/wally-pipelined/testbench/testbench-imperas.sv
+++ b/wally-pipelined/testbench/testbench-imperas.sv
@@ -543,10 +543,10 @@ string tests32f[] = '{
         if (`C_SUPPORTED) tests = {tests, tests64ic};
         else              tests = {tests, tests64iNOc};
         if (`M_SUPPORTED) tests = {tests, tests64m};
-        if (`MEM_VIRTMEM) tests = {tests, tests64mmu};
         //if (`A_SUPPORTED) tests = {tests, tests64a};
         if (`F_SUPPORTED) tests = {tests64f, tests};
         if (`D_SUPPORTED) tests = {tests64d, tests};
+        if (`MEM_VIRTMEM) tests = {tests64mmu, tests};
       end
       //tests = {tests64a, tests};
     end else begin // RV32