mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Updated Dcache to fully support flush. This appears to work.
Updated PCNextF so it points to the correct PC after icache invalidate. Build root crashes with PCW mismatch and invalid register writes.
This commit is contained in:
Ross Thompson
parent
d4398c23fb
commit
b92070a67a
@ -14,41 +14,41 @@ add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM
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add wave -noupdate -expand -group {WriteBack stage} /testbench/dut/hart/ieu/InstrValidW
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add wave -noupdate -expand -group {WriteBack stage} /testbench/dut/hart/ieu/InstrValidW
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add wave -noupdate -expand -group {WriteBack stage} /testbench/PCW
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add wave -noupdate -expand -group {WriteBack stage} /testbench/PCW
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
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add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
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add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
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add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/RetM
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add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -expand -group HDU -group hazards -color Pink /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/StoreStallD
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/StoreStallD
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/ICacheStallF
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LSUStall
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/MulDivStallD
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
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add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD
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add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE
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add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM
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add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW
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add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
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add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/hart/StallF
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
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add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/hart/StallD
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
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add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/hart/StallE
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
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add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/hart/StallM
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
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add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/hart/StallW
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add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
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add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
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@ -129,18 +129,18 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/a
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/b
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/result
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/flags
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/flags
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add wave -noupdate -expand -group alu -divider internals
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add wave -noupdate -group alu -divider internals
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/overflow
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/carry
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/zero
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/neg
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/lt
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt
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add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/ltu
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add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E
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add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E
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@ -188,11 +188,12 @@ add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/controll
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/ITLBMissF
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/ITLBMissF
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ReadLineF
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ReadLineF
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add wave -noupdate -expand -group icache {/testbench/dut/hart/ifu/icache/icachemem/word[0]/CacheDataMem/Addr}
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add wave -noupdate -expand -group icache {/testbench/dut/hart/ifu/icache/icachemem/word[0]/CacheDataMem/WriteData}
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add wave -noupdate -expand -group icache {/testbench/dut/hart/ifu/icache/icachemem/word[0]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/PCNextIndexF
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/PCNextIndexF
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ReadLineF
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add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ReadLineF
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add wave -noupdate -expand -group icache {/testbench/dut/hart/ifu/icache/MemWay[0]/ValidBits}
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add wave -noupdate -expand -group icache {/testbench/dut/hart/ifu/icache/MemWay[1]/ValidBits}
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add wave -noupdate -expand -group icache {/testbench/dut/hart/ifu/icache/MemWay[2]/ValidBits}
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add wave -noupdate -expand -group icache {/testbench/dut/hart/ifu/icache/MemWay[3]/ValidBits}
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
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add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
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@ -241,70 +242,78 @@ add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcac
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWayWriteEnableM
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWayWriteEnableM
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
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add wave -noupdate -group lsu -expand -group dcache -expand -group flush -radix unsigned /testbench/dut/hart/lsu/dcache/FlushAdr
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add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/hart/lsu/dcache/FlushWay
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add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/hart/lsu/dcache/VictimDirtyWay
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add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/hart/lsu/dcache/VictimTag
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add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/hart/lsu/dcache/BasePAdrM
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WriteEnable}
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add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WriteEnable}
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetValid}
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add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetValid}
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetDirty}
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add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetDirty}
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[0]/CacheTagMem/StoredData}
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add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[0]/CacheTagMem/StoredData}
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/DirtyBits}
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add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/DirtyBits}
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ValidBits}
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add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ValidBits}
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
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add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
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add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
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add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
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add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
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add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/DirtyBits}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/DirtyBits}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/SetDirty}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ValidBits}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/SetDirty}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteWordEnable}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteEnable}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[1]/CacheTagMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteWordEnable}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[1]/CacheTagMem/StoredData}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetValid}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WriteEnable}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetDirty}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetValid}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[2]/CacheTagMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetDirty}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/DirtyBits}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[2]/CacheTagMem/StoredData}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ValidBits}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/DirtyBits}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ValidBits}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetValid}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WriteEnable}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetDirty}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetValid}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[3]/CacheTagMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetDirty}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/DirtyBits}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ClearDirty}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ValidBits}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/VDWriteEnable}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[3]/CacheTagMem/StoredData}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/DirtyBits}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ValidBits}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/SetValid
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearValid
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/SetDirty
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearDirty
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetValid
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WayHit}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearValid
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Valid}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetDirty
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Dirty}
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearDirty
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ReadTag}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WayHit}
|
||||||
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Valid}
|
||||||
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Dirty}
|
||||||
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ReadTag}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WayHit}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WayHit}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Valid}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Valid}
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Dirty}
|
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Dirty}
|
||||||
@ -338,12 +347,13 @@ add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench
|
|||||||
add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
|
add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
|
add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/FetchCount
|
add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/FetchCount
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA
|
||||||
add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA
|
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA
|
||||||
|
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/FlushWay
|
||||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode
|
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode
|
||||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate
|
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate
|
||||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation
|
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation
|
||||||
@ -496,7 +506,7 @@ add wave -noupdate /testbench/dut/hart/ieu/c/BranchE
|
|||||||
add wave -noupdate /testbench/dut/hart/ifu/PCTargetE
|
add wave -noupdate /testbench/dut/hart/ifu/PCTargetE
|
||||||
add wave -noupdate /testbench/dut/hart/ifu/PCLinkE
|
add wave -noupdate /testbench/dut/hart/ifu/PCLinkE
|
||||||
TreeUpdate [SetDefaultTree]
|
TreeUpdate [SetDefaultTree]
|
||||||
WaveRestoreCursors {{Cursor 6} {160470606 ns} 0} {{Cursor 21} {161371350 ns} 0} {{Cursor 22} {72228581 ns} 0} {{Cursor 23} {11297671 ns} 0}
|
WaveRestoreCursors {{Cursor 23} {8699 ns} 0} {{Cursor 5} {3318 ns} 0}
|
||||||
quietly wave cursor active 1
|
quietly wave cursor active 1
|
||||||
configure wave -namecolwidth 250
|
configure wave -namecolwidth 250
|
||||||
configure wave -valuecolwidth 354
|
configure wave -valuecolwidth 354
|
||||||
@ -512,4 +522,4 @@ configure wave -griddelta 40
|
|||||||
configure wave -timeline 0
|
configure wave -timeline 0
|
||||||
configure wave -timelineunits ns
|
configure wave -timelineunits ns
|
||||||
update
|
update
|
||||||
WaveRestoreZoom {160470352 ns} {160470676 ns}
|
WaveRestoreZoom {8629 ns} {8783 ns}
|
||||||
|
|||||||
@ -38,6 +38,7 @@ switch $argc {
|
|||||||
vopt -fsmdebug +acc -gDEBUG=1 work.testbench -o workopt
|
vopt -fsmdebug +acc -gDEBUG=1 work.testbench -o workopt
|
||||||
vsim workopt -fsmdebug
|
vsim workopt -fsmdebug
|
||||||
|
|
||||||
|
#profile on
|
||||||
|
|
||||||
do wave.do
|
do wave.do
|
||||||
add log -r /*
|
add log -r /*
|
||||||
|
|||||||
18
wally-pipelined/src/cache/cacheway.sv
vendored
18
wally-pipelined/src/cache/cacheway.sv
vendored
@ -34,6 +34,7 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
|
|||||||
input logic [$clog2(NUMLINES)-1:0] WAdr,
|
input logic [$clog2(NUMLINES)-1:0] WAdr,
|
||||||
input logic [`PA_BITS-1:0] PAdr,
|
input logic [`PA_BITS-1:0] PAdr,
|
||||||
input logic WriteEnable,
|
input logic WriteEnable,
|
||||||
|
input logic VDWriteEnable,
|
||||||
input logic [BLOCKLEN/`XLEN-1:0] WriteWordEnable,
|
input logic [BLOCKLEN/`XLEN-1:0] WriteWordEnable,
|
||||||
input logic TagWriteEnable,
|
input logic TagWriteEnable,
|
||||||
input logic [BLOCKLEN-1:0] WriteData,
|
input logic [BLOCKLEN-1:0] WriteData,
|
||||||
@ -59,6 +60,8 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
|
|||||||
logic Valid;
|
logic Valid;
|
||||||
logic Dirty;
|
logic Dirty;
|
||||||
logic SelectedWay;
|
logic SelectedWay;
|
||||||
|
logic [TAGLEN-1:0] VicDirtyWay;
|
||||||
|
logic [TAGLEN-1:0] FlushThisWay;
|
||||||
|
|
||||||
genvar words;
|
genvar words;
|
||||||
|
|
||||||
@ -89,16 +92,23 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
|
|||||||
|
|
||||||
assign VictimDirtyWay = SelFlush ? FlushWay & Dirty & Valid :
|
assign VictimDirtyWay = SelFlush ? FlushWay & Dirty & Valid :
|
||||||
VictimWay & Dirty & Valid;
|
VictimWay & Dirty & Valid;
|
||||||
|
/* -----\/----- EXCLUDED -----\/-----
|
||||||
assign VictimTagWay = SelFlush & FlushWay ? ReadTag :
|
assign VictimTagWay = SelFlush & FlushWay ? ReadTag :
|
||||||
VictimWay ? ReadTag : '0;
|
VictimWay ? ReadTag : '0;
|
||||||
|
-----/\----- EXCLUDED -----/\----- */
|
||||||
|
|
||||||
|
assign VicDirtyWay = VictimWay ? ReadTag : '0;
|
||||||
|
assign FlushThisWay = FlushWay ? ReadTag : '0;
|
||||||
|
assign VictimTagWay = SelFlush ? FlushThisWay : VicDirtyWay;
|
||||||
|
|
||||||
|
|
||||||
always_ff @(posedge clk, posedge reset) begin
|
always_ff @(posedge clk, posedge reset) begin
|
||||||
if (reset)
|
if (reset)
|
||||||
ValidBits <= {NUMLINES{1'b0}};
|
ValidBits <= {NUMLINES{1'b0}};
|
||||||
else if (InvalidateAll)
|
else if (InvalidateAll)
|
||||||
ValidBits <= {NUMLINES{1'b0}};
|
ValidBits <= {NUMLINES{1'b0}};
|
||||||
else if (SetValid & WriteEnable) ValidBits[WAdr] <= 1'b1;
|
else if (SetValid & (WriteEnable | VDWriteEnable)) ValidBits[WAdr] <= 1'b1;
|
||||||
else if (ClearValid & WriteEnable) ValidBits[WAdr] <= 1'b0;
|
else if (ClearValid & (WriteEnable | VDWriteEnable)) ValidBits[WAdr] <= 1'b0;
|
||||||
Valid <= ValidBits[RAdr];
|
Valid <= ValidBits[RAdr];
|
||||||
end
|
end
|
||||||
|
|
||||||
@ -107,8 +117,8 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
|
|||||||
always_ff @(posedge clk, posedge reset) begin
|
always_ff @(posedge clk, posedge reset) begin
|
||||||
if (reset)
|
if (reset)
|
||||||
DirtyBits <= {NUMLINES{1'b0}};
|
DirtyBits <= {NUMLINES{1'b0}};
|
||||||
else if (SetDirty & WriteEnable) DirtyBits[WAdr] <= 1'b1;
|
else if (SetDirty & (WriteEnable | VDWriteEnable)) DirtyBits[WAdr] <= 1'b1;
|
||||||
else if (ClearDirty & WriteEnable) DirtyBits[WAdr] <= 1'b0;
|
else if (ClearDirty & (WriteEnable | VDWriteEnable)) DirtyBits[WAdr] <= 1'b0;
|
||||||
Dirty <= DirtyBits[RAdr];
|
Dirty <= DirtyBits[RAdr];
|
||||||
end
|
end
|
||||||
end else begin
|
end else begin
|
||||||
|
|||||||
12
wally-pipelined/src/cache/dcache.sv
vendored
12
wally-pipelined/src/cache/dcache.sv
vendored
@ -141,6 +141,7 @@ module dcache
|
|||||||
logic FlushWayCntRst;
|
logic FlushWayCntRst;
|
||||||
|
|
||||||
logic SelFlush;
|
logic SelFlush;
|
||||||
|
logic VDWriteEnable;
|
||||||
|
|
||||||
logic AnyCPUReqM;
|
logic AnyCPUReqM;
|
||||||
logic FetchCountFlag;
|
logic FetchCountFlag;
|
||||||
@ -176,6 +177,7 @@ module dcache
|
|||||||
.WAdr,
|
.WAdr,
|
||||||
.PAdr(MemPAdrM[`PA_BITS-1:0]),
|
.PAdr(MemPAdrM[`PA_BITS-1:0]),
|
||||||
.WriteEnable(SRAMWayWriteEnable),
|
.WriteEnable(SRAMWayWriteEnable),
|
||||||
|
.VDWriteEnable,
|
||||||
.WriteWordEnable(SRAMWordEnable),
|
.WriteWordEnable(SRAMWordEnable),
|
||||||
.TagWriteEnable(SRAMBlockWayWriteEnableM),
|
.TagWriteEnable(SRAMBlockWayWriteEnableM),
|
||||||
.WriteData(SRAMWriteData),
|
.WriteData(SRAMWriteData),
|
||||||
@ -292,9 +294,10 @@ module dcache
|
|||||||
end
|
end
|
||||||
endgenerate
|
endgenerate
|
||||||
|
|
||||||
mux2 #(`PA_BITS) BaseAdrMux(.d0(MemPAdrM),
|
mux3 #(`PA_BITS) BaseAdrMux(.d0(MemPAdrM),
|
||||||
.d1({VictimTag, MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
|
.d1({VictimTag, MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
|
||||||
.s(SelEvict | SelFlush),
|
.d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}),
|
||||||
|
.s({SelFlush, SelEvict}),
|
||||||
.y(BasePAdrM));
|
.y(BasePAdrM));
|
||||||
|
|
||||||
// if not cacheable the offset bits needs to be sent to the EBU.
|
// if not cacheable the offset bits needs to be sent to the EBU.
|
||||||
@ -324,6 +327,8 @@ module dcache
|
|||||||
.en(FlushAdrCntEn & FlushWay[NUMWAYS-1]),
|
.en(FlushAdrCntEn & FlushWay[NUMWAYS-1]),
|
||||||
.d(FlushAdrP1),
|
.d(FlushAdrP1),
|
||||||
.q(FlushAdr));
|
.q(FlushAdr));
|
||||||
|
assign FlushAdrP1 = FlushAdr + 1'b1;
|
||||||
|
|
||||||
|
|
||||||
flopenl #(NUMWAYS)
|
flopenl #(NUMWAYS)
|
||||||
FlushWayReg(.clk,
|
FlushWayReg(.clk,
|
||||||
@ -333,6 +338,8 @@ module dcache
|
|||||||
.d(NextFlushWay),
|
.d(NextFlushWay),
|
||||||
.q(FlushWay));
|
.q(FlushWay));
|
||||||
|
|
||||||
|
assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]};
|
||||||
|
|
||||||
assign FlushAdrFlag = FlushAdr == FlushAdrThreshold[INDEXLEN-1:0] & FlushWay[NUMWAYS-1];
|
assign FlushAdrFlag = FlushAdr == FlushAdrThreshold[INDEXLEN-1:0] & FlushWay[NUMWAYS-1];
|
||||||
|
|
||||||
|
|
||||||
@ -384,6 +391,7 @@ module dcache
|
|||||||
.FlushWayCntRst,
|
.FlushWayCntRst,
|
||||||
.FlushAdrFlag,
|
.FlushAdrFlag,
|
||||||
.FlushDCacheM,
|
.FlushDCacheM,
|
||||||
|
.VDWriteEnable,
|
||||||
.LRUWriteEn);
|
.LRUWriteEn);
|
||||||
|
|
||||||
|
|
||||||
|
|||||||
27
wally-pipelined/src/cache/dcachefsm.sv
vendored
27
wally-pipelined/src/cache/dcachefsm.sv
vendored
@ -83,7 +83,8 @@ module dcachefsm
|
|||||||
output logic FlushAdrCntEn,
|
output logic FlushAdrCntEn,
|
||||||
output logic FlushWayCntEn,
|
output logic FlushWayCntEn,
|
||||||
output logic FlushAdrCntRst,
|
output logic FlushAdrCntRst,
|
||||||
output logic FlushWayCntRst
|
output logic FlushWayCntRst,
|
||||||
|
output logic VDWriteEnable
|
||||||
|
|
||||||
);
|
);
|
||||||
|
|
||||||
@ -184,6 +185,7 @@ module dcachefsm
|
|||||||
FlushWayCntEn = 1'b0;
|
FlushWayCntEn = 1'b0;
|
||||||
FlushAdrCntRst = 1'b0;
|
FlushAdrCntRst = 1'b0;
|
||||||
FlushWayCntRst = 1'b0;
|
FlushWayCntRst = 1'b0;
|
||||||
|
VDWriteEnable = 1'b0;
|
||||||
NextState = STATE_READY;
|
NextState = STATE_READY;
|
||||||
|
|
||||||
case (CurrState)
|
case (CurrState)
|
||||||
@ -869,14 +871,20 @@ module dcachefsm
|
|||||||
STATE_FLUSH: begin
|
STATE_FLUSH: begin
|
||||||
DCacheStall = 1'b1;
|
DCacheStall = 1'b1;
|
||||||
CommittedM = 1'b1;
|
CommittedM = 1'b1;
|
||||||
FlushAdrCntEn = 1'b1;
|
|
||||||
FlushWayCntEn = 1'b1;
|
|
||||||
SelAdrM = 2'b11;
|
SelAdrM = 2'b11;
|
||||||
SelFlush = 1'b1;
|
SelFlush = 1'b1;
|
||||||
|
FlushAdrCntEn = 1'b1;
|
||||||
|
FlushWayCntEn = 1'b1;
|
||||||
|
CntReset = 1'b1;
|
||||||
if(VictimDirty) begin
|
if(VictimDirty) begin
|
||||||
NextState = STATE_FLUSH_WRITE_BACK;
|
NextState = STATE_FLUSH_WRITE_BACK;
|
||||||
|
FlushAdrCntEn = 1'b0;
|
||||||
|
FlushWayCntEn = 1'b0;
|
||||||
end else if (FlushAdrFlag) begin
|
end else if (FlushAdrFlag) begin
|
||||||
NextState = STATE_READY;
|
NextState = STATE_READY;
|
||||||
|
DCacheStall = 1'b0;
|
||||||
|
FlushAdrCntEn = 1'b0;
|
||||||
|
FlushWayCntEn = 1'b0;
|
||||||
end else begin
|
end else begin
|
||||||
NextState = STATE_FLUSH;
|
NextState = STATE_FLUSH;
|
||||||
end
|
end
|
||||||
@ -884,27 +892,34 @@ module dcachefsm
|
|||||||
|
|
||||||
STATE_FLUSH_WRITE_BACK: begin
|
STATE_FLUSH_WRITE_BACK: begin
|
||||||
DCacheStall = 1'b1;
|
DCacheStall = 1'b1;
|
||||||
PreCntEn = 1'b1;
|
|
||||||
AHBWrite = 1'b1;
|
AHBWrite = 1'b1;
|
||||||
SelAdrM = 2'b11;
|
SelAdrM = 2'b11;
|
||||||
CommittedM = 1'b1;
|
CommittedM = 1'b1;
|
||||||
SelFlush = 1'b1;
|
SelFlush = 1'b1;
|
||||||
|
PreCntEn = 1'b1;
|
||||||
if(FetchCountFlag & AHBAck) begin
|
if(FetchCountFlag & AHBAck) begin
|
||||||
NextState = STATE_FLUSH_WRITE_BACK;
|
|
||||||
end else begin
|
|
||||||
NextState = STATE_FLUSH_CLEAR_DIRTY;
|
NextState = STATE_FLUSH_CLEAR_DIRTY;
|
||||||
|
end else begin
|
||||||
|
NextState = STATE_FLUSH_WRITE_BACK;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
STATE_FLUSH_CLEAR_DIRTY: begin
|
STATE_FLUSH_CLEAR_DIRTY: begin
|
||||||
DCacheStall = 1'b1;
|
DCacheStall = 1'b1;
|
||||||
ClearDirty = 1'b1;
|
ClearDirty = 1'b1;
|
||||||
|
VDWriteEnable = 1'b1;
|
||||||
SelFlush = 1'b1;
|
SelFlush = 1'b1;
|
||||||
SelAdrM = 2'b11;
|
SelAdrM = 2'b11;
|
||||||
|
FlushAdrCntEn = 1'b0;
|
||||||
|
FlushWayCntEn = 1'b0;
|
||||||
if(FlushAdrFlag) begin
|
if(FlushAdrFlag) begin
|
||||||
NextState = STATE_READY;
|
NextState = STATE_READY;
|
||||||
|
DCacheStall = 1'b0;
|
||||||
|
SelAdrM = 2'b00;
|
||||||
end else begin
|
end else begin
|
||||||
NextState = STATE_FLUSH;
|
NextState = STATE_FLUSH;
|
||||||
|
FlushAdrCntEn = 1'b1;
|
||||||
|
FlushWayCntEn = 1'b1;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|||||||
1
wally-pipelined/src/cache/icache.sv
vendored
1
wally-pipelined/src/cache/icache.sv
vendored
@ -144,6 +144,7 @@ module icache
|
|||||||
.WAdr(PCTagF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
.WAdr(PCTagF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
||||||
.PAdr(PCTagF),
|
.PAdr(PCTagF),
|
||||||
.WriteEnable(SRAMWayWriteEnable),
|
.WriteEnable(SRAMWayWriteEnable),
|
||||||
|
.VDWriteEnable(1'b0),
|
||||||
.WriteWordEnable({{(BLOCKLEN/`XLEN){1'b1}}}),
|
.WriteWordEnable({{(BLOCKLEN/`XLEN){1'b1}}}),
|
||||||
.TagWriteEnable(SRAMWayWriteEnable),
|
.TagWriteEnable(SRAMWayWriteEnable),
|
||||||
.WriteData(ICacheMemWriteData),
|
.WriteData(ICacheMemWriteData),
|
||||||
|
|||||||
@ -173,11 +173,16 @@ module ifu (
|
|||||||
.y(PCNext1F));
|
.y(PCNext1F));
|
||||||
|
|
||||||
mux2 #(`XLEN) pcmux2(.d0(PCNext1F),
|
mux2 #(`XLEN) pcmux2(.d0(PCNext1F),
|
||||||
.d1(PrivilegedNextPCM),
|
.d1(PCE),
|
||||||
.s(PrivilegedChangePCM),
|
.s(InvalidateICacheM),
|
||||||
.y(PCNext2F));
|
.y(PCNext2F));
|
||||||
|
|
||||||
mux2 #(`XLEN) pcmux4(.d0(PCNext2F),
|
mux2 #(`XLEN) pcmux3(.d0(PCNext2F),
|
||||||
|
.d1(PrivilegedNextPCM),
|
||||||
|
.s(PrivilegedChangePCM),
|
||||||
|
.y(PCNext3F));
|
||||||
|
|
||||||
|
mux2 #(`XLEN) pcmux4(.d0(PCNext3F),
|
||||||
.d1(`RESET_VECTOR),
|
.d1(`RESET_VECTOR),
|
||||||
.s(reset_q),
|
.s(reset_q),
|
||||||
.y(UnalignedPCNextF));
|
.y(UnalignedPCNextF));
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user