From eb337fd3e1fd115fbc57c38e941bf738d8df575d Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Mon, 28 Mar 2022 19:11:45 +0000 Subject: [PATCH 1/2] added test config that doesn't use compressed instructions for privileged tests --- pipelined/regression/regression-wally | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/pipelined/regression/regression-wally b/pipelined/regression/regression-wally index c638ed3c2..a5535b49b 100755 --- a/pipelined/regression/regression-wally +++ b/pipelined/regression/regression-wally @@ -70,7 +70,7 @@ for test in tests64gc: cmd="vsim > {} -c < {} -c < {} -c < Date: Mon, 28 Mar 2022 19:12:22 +0000 Subject: [PATCH 2/2] fixed double multiplication on vectored interrupts --- pipelined/src/privileged/trap.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv index 15c1e9e63..b2d6fea96 100644 --- a/pipelined/src/privileged/trap.sv +++ b/pipelined/src/privileged/trap.sv @@ -102,7 +102,7 @@ module trap ( if(`VECTORED_INTERRUPTS_SUPPORTED) begin:vec always_comb if (PrivilegedTrapVector[1:0] == 2'b01 & CauseM[`XLEN-1] == 1) - PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2] + {CauseM[`XLEN-5:0], 2'b00}, 2'b00}; + PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2] + CauseM[`XLEN-5:0], 2'b00}; else PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2], 2'b00}; end