diff --git a/pipelined/src/ebu/ahblite.sv b/pipelined/src/ebu/ahblite.sv
index 4203f0f52..be7f789e4 100644
--- a/pipelined/src/ebu/ahblite.sv
+++ b/pipelined/src/ebu/ahblite.sv
@@ -157,7 +157,7 @@ module ahblite (
   assign HMASTLOCK = 0; // no locking supported
   assign HWRITE = (NextBusState == MEMWRITE);
   // Byte mask for HWSTRB
-  swbytemask swbytemask(.Size(HSIZED[1:0]), .Adr(HADDRD[2:0]), .ByteMask(HWSTRB));
+  swbytemask #(`XLEN) swbytemask(.Size(HSIZED[2:0]), .Adr(HADDRD[$clog2(`XLEN/8)-1:0]), .ByteMask(HWSTRB));
 
   // delay write data by one cycle for
   flopen #(`XLEN) wdreg(HCLK, (LSUBusAck | LSUBusInit), LSUBusHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index fe5447c4f..d472a80fd 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -279,7 +279,7 @@ module lsu (
     .LSUFunct3M, .AMOWriteDataM, .LittleEndianWriteDataM);
 
   // Compute byte masks
-  swbytemaskword #(`LLEN) swbytemask(.Size(LSUFunct3M), .Adr(LSUPAdrM[$clog2(`LLEN/8)-1:0]), .ByteMask(ByteMaskM));
+  swbytemask #(`LLEN) swbytemask(.Size(LSUFunct3M), .Adr(LSUPAdrM[$clog2(`LLEN/8)-1:0]), .ByteMask(ByteMaskM));
 
   /////////////////////////////////////////////////////////////////////////////////////////////
   // MW Pipeline Register
diff --git a/pipelined/src/lsu/swbytemask.sv b/pipelined/src/lsu/swbytemask.sv
index 7f89e628a..faae408e9 100644
--- a/pipelined/src/lsu/swbytemask.sv
+++ b/pipelined/src/lsu/swbytemask.sv
@@ -30,13 +30,15 @@
 
 `include "wally-config.vh"
 
-module swbytemask (
-  input logic [1:0]         Size,
-  input logic [2:0]         Adr,
-  output logic [`XLEN/8-1:0] ByteMask);
-  
+module swbytemask #(parameter WORDLEN = 64)(
+  input logic [2:0]              Size,
+  input logic [$clog2(WORDLEN/8)-1:0] Adr,
+  output logic [WORDLEN/8-1:0]   ByteMask);
 
-  if(`XLEN == 64) begin
+  assign ByteMask = ((2**(2**Size))-1) << Adr;
+
+/* Equivalent to the following for WORDLEN = 64
+ if(WORDLEN == 64) begin
     always_comb begin
       case(Size[1:0])
         2'b00: begin ByteMask = 8'b00000000; ByteMask[Adr[2:0]] = 1; end // sb
@@ -49,18 +51,10 @@ module swbytemask (
         2'b10: if (Adr[2]) ByteMask = 8'b11110000;
                else        ByteMask = 8'b00001111;
         2'b11: ByteMask = 8'b1111_1111;
-      endcase
-    end
-  end else begin
-    always_comb begin
-      case(Size[1:0])
-        2'b00: begin ByteMask = 4'b0000; ByteMask[Adr[1:0]] = 1; end // sb
-        2'b01: if (Adr[1]) ByteMask = 4'b1100;
-               else        ByteMask = 4'b0011;
-        2'b10: ByteMask = 4'b1111;
-        default: ByteMask =  4'b1111;
+        default ByteMask = 8'b0000_0000;
       endcase
     end
   end
+*/
 
 endmodule