Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

added BRegWriteE signal

Browse Source
This commit is contained in:
Kevin Kim 2023-03-02 12:15:22 -08:00
parent 5e10720bed
commit b81a5e4452
1 changed files with 3 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/ieu/bmu/bmuctrl.sv
View File

@ -45,7 +45,8 @@ module bmuctrl(
input logic StallE, FlushE, // Stall, flush Execute stage
output logic [2:0] ALUSelectE,
output logic [3:0] BSelectE, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding
output logic [2:0] ZBBSelectE // ZBB mux select signal
output logic [2:0] ZBBSelectE, // ZBB mux select signal
output logic BRegWriteE // Indicates if it is a R type B instruction in Execute
);
logic [6:0] OpD; // Opcode in Decode stage
@ -159,5 +160,5 @@ module bmuctrl(
// BMU Execute stage pipieline control register
flopenrc#(10) controlregBMU(clk, reset, FlushE, ~StallE, {ALUSelectD, BSelectD, ZBBSelectD}, {ALUSelectE, BSelectE, ZBBSelectE});
flopenrc#(11) controlregBMU(clk, reset, FlushE, ~StallE, {ALUSelectD, BSelectD, ZBBSelectD, BRegWriteD}, {ALUSelectE, BSelectE, ZBBSelectE, BRegWriteE});
endmodule