From b7f4e72eec809444a3809b2585e746b26be9d7a8 Mon Sep 17 00:00:00 2001 From: Noah Boorstin Date: Wed, 24 Feb 2021 02:02:28 +0000 Subject: [PATCH] busybear: add bootram section in the same manner as ram --- .../testbench/testbench-busybear.sv | 20 +++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/wally-pipelined/testbench/testbench-busybear.sv b/wally-pipelined/testbench/testbench-busybear.sv index dc4d91587..cf19857af 100644 --- a/wally-pipelined/testbench/testbench-busybear.sv +++ b/wally-pipelined/testbench/testbench-busybear.sv @@ -165,10 +165,11 @@ module testbench_busybear(); endgenerate logic [`XLEN-1:0] RAM[('h8000000 >> 3):0]; + logic [`XLEN-1:0] bootram[('h2000 >> 3):0]; logic [`XLEN-1:0] readRAM, readPC; integer RAMAdr, RAMPC; - assign RAMAdr = (HADDR - 'h80000000) >> 3; - assign RAMPC = (PCF - 'h80000000) >> 3; + assign RAMAdr = (HADDR - (HADDR > 'h2fff ? 'h80000000 : 'h1000)) >> 3; + assign RAMPC = (PCF - (PCF > 'h2fff ? 'h80000000 : 'h1000)) >> 3; logic [63:0] readMask; assign readMask = ((1 << (8*(1 << HSIZE))) - 1) << 8 * HADDR[2:0]; always @(HWDATA or HADDR or HSIZE or HWRITE or dut.hart.MemRWM[1]) begin @@ -185,6 +186,21 @@ module testbench_busybear(); readPC = RAM[RAMPC]; end end + // there's almost certianly a better way than just copying this, but its simple enough for now: + always @(HWDATA or HADDR or HSIZE or HWRITE or dut.hart.MemRWM[1]) begin + if ((HWRITE || dut.hart.MemRWM[1]) && (HADDR >= 'h1000 && HADDR <= 'h2FFF)) begin + if (HWRITE) begin + bootram[RAMAdr] = (bootram[RAMAdr] & (~readMask)) | ((HWDATA << 8 * HADDR[2:0]) & readMask); + end else begin + readRAM = bootram[RAMAdr] & readMask; + end + end + end + always @(PCF) begin + if (PCF >= 'h1000 && PCF <= 'h2FFF) begin + readPC = bootram[RAMPC]; + end + end logic [`XLEN-1:0] readAdrExpected; // this might need to change