From b7e66ec7d6f8272deddf5499f67ae9fc935a9144 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 20 Apr 2024 13:17:33 -0700 Subject: [PATCH] Added Zcb tests to riscof --- tests/riscof/sail_cSim/riscof_sail_cSim.py | 6 +++++- tests/riscof/spike/spike_rv32gc_isa.yaml | 6 ++---- tests/riscof/spike/spike_rv64gc_isa.yaml | 4 +--- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/tests/riscof/sail_cSim/riscof_sail_cSim.py b/tests/riscof/sail_cSim/riscof_sail_cSim.py index 878e25d4f..eeb024d36 100644 --- a/tests/riscof/sail_cSim/riscof_sail_cSim.py +++ b/tests/riscof/sail_cSim/riscof_sail_cSim.py @@ -52,6 +52,7 @@ class sail_cSim(pluginTemplate): ispec = utils.load_yaml(isa_yaml)['hart0'] self.xlen = ('64' if 64 in ispec['supported_xlen'] else '32') self.isa = 'rv' + self.xlen + self.sailargs = ' ' self.compile_cmd = self.compile_cmd+' -mabi='+('lp64 ' if 64 in ispec['supported_xlen'] else ('ilp32e ' if "E" in ispec["ISA"] else 'ilp32 ')) if "I" in ispec["ISA"]: self.isa += 'i' @@ -67,6 +68,8 @@ class sail_cSim(pluginTemplate): self.isa += 'f' if "D" in ispec["ISA"]: self.isa += 'd' + if "Zcb" in ispec["ISA"]: # for some strange reason, Sail requires a command line argument to enable Zcb + self.sailargs += "--enable-zcb" objdump = "riscv64-unknown-elf-objdump".format(self.xlen) if shutil.which(objdump) is None: logger.error(objdump+": executable not found. Please check environment setup.") @@ -112,7 +115,8 @@ class sail_cSim(pluginTemplate): reference_output = re.sub("/src/","/references/", re.sub(".S",".reference_output", test)) execute += 'cut -c-{0:g} {1} > {2}'.format(8, reference_output, sig_file) #use cut to remove comments when copying else: - execute += self.sail_exe[self.xlen] + ' -z268435455 -i --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name) + execute += self.sail_exe[self.xlen] + ' -z268435455 -i ' + self.sailargs + ' --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name) +# execute += self.sail_exe[self.xlen] + ' -z268435455 -i --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name) cov_str = ' ' for label in testentry['coverage_labels']: diff --git a/tests/riscof/spike/spike_rv32gc_isa.yaml b/tests/riscof/spike/spike_rv32gc_isa.yaml index 1879440ed..1e2474023 100644 --- a/tests/riscof/spike/spike_rv32gc_isa.yaml +++ b/tests/riscof/spike/spike_rv32gc_isa.yaml @@ -1,8 +1,6 @@ hart_ids: [0] hart0: - ISA: RV32IMAFDCZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh -# ISA: RV32IMAFDCZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbs -# ISA: RV32IMAFDCZicsr_Zicboz_Zifencei_Zca_Zba_Zbb_Zbc_Zbs # _Zbkb_Zcb + ISA: RV32IMAFDCZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh physical_addr_sz: 32 User_Spec_Version: '2.3' supported_xlen: [32] @@ -27,4 +25,4 @@ hart0: legal: - extensions[25:0] bitmask [0x000112D, 0x0000000] wr_illegal: - - Unchanged \ No newline at end of file + - Unchangedcd \ No newline at end of file diff --git a/tests/riscof/spike/spike_rv64gc_isa.yaml b/tests/riscof/spike/spike_rv64gc_isa.yaml index b8fabebde..5b3f2f47d 100644 --- a/tests/riscof/spike/spike_rv64gc_isa.yaml +++ b/tests/riscof/spike/spike_rv64gc_isa.yaml @@ -1,8 +1,6 @@ hart_ids: [0] hart0: -# ISA: RV64IMAFDCSUZicsr_Zicboz_Zifencei_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb -# ISA: RV64IMAFDCSUZicsr_Zifencei_Zca_Zcb_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb - ISA: RV64IMAFDQCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh + ISA: RV64IMAFDQCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh physical_addr_sz: 56 User_Spec_Version: '2.3' supported_xlen: [64]