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Reset Vector moved to config file

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This commit is contained in:
David Harris 2021-01-25 15:57:36 -05:00
parent a54070d074
commit b7988e536f
6 changed files with 13 additions and 10 deletions
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3
wally-pipelined/config/rv32ic/wally-config.vh
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@ -54,6 +54,9 @@
`define MEM_ICACHE 0 `define MEM_ICACHE 0
`define MEM_VIRTMEM 0 `define MEM_VIRTMEM 0
// Address space
`define RESET_VECTOR 32'h80000000
// Test modes // Test modes
// Tie GPIO outputs back to inputs // Tie GPIO outputs back to inputs

3
wally-pipelined/config/rv64ic/wally-config.vh
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@ -54,6 +54,9 @@
`define MEM_ICACHE 0 `define MEM_ICACHE 0
`define MEM_VIRTMEM 0 `define MEM_VIRTMEM 0
// Address space
`define RESET_VECTOR 64'h0000000080000000
// Test modes // Test modes
// Tie GPIO outputs back to inputs // Tie GPIO outputs back to inputs

2
wally-pipelined/lint-wally
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@ -1 +1 @@
verilator --lint-only -Isrc src/*.sv verilator --lint-only -Iconfig/rv64ic src/*.sv

4
wally-pipelined/src/datapath.sv
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@ -25,7 +25,7 @@
`include "wally-config.vh" `include "wally-config.vh"
module datapath #(parameter PCSTART = 32'h80000000) ( module datapath (
input logic clk, reset, input logic clk, reset,
// Fetch stage signals // Fetch stage signals
input logic StallF, input logic StallF,
@ -110,7 +110,7 @@ module datapath #(parameter PCSTART = 32'h80000000) (
logic [31:0] nop = 32'h00000013; // instruction for NOP logic [31:0] nop = 32'h00000013; // instruction for NOP
// Fetch stage pipeline register and logic; also Ex stage for branches // Fetch stage pipeline register and logic; also Ex stage for branches
pclogic #(PCSTART) pclogic(.*); pclogic pclogic(.*);
// Decode stage pipeline register and logic // Decode stage pipeline register and logic
flopenl #(32) InstrDReg(clk, reset, ~StallD, (FlushD ? nop : InstrF), nop, InstrD); flopenl #(32) InstrDReg(clk, reset, ~StallD, (FlushD ? nop : InstrF), nop, InstrD);

7
wally-pipelined/src/pclogic.sv
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@ -25,7 +25,7 @@
`include "wally-config.vh" `include "wally-config.vh"
module pclogic #(parameter PCSTART) ( module pclogic (
input logic clk, reset, input logic clk, reset,
input logic StallF, PCSrcE, input logic StallF, PCSrcE,
input logic [31:0] InstrF, input logic [31:0] InstrF,
@ -37,9 +37,6 @@ module pclogic #(parameter PCSTART) (
output logic [`XLEN-1:0] InstrMisalignedAdrM); output logic [`XLEN-1:0] InstrMisalignedAdrM);
logic [`XLEN-1:0] UnalignedPCNextF, PCNextF, PCTargetE; logic [`XLEN-1:0] UnalignedPCNextF, PCNextF, PCTargetE;
// logic [`XLEN-1:0] ResetVector = 'h100;
// logic [`XLEN-1:0] ResetVector = 'he4;
logic [`XLEN-1:0] ResetVector = {{(`XLEN-32){1'b0}}, PCSTART};
logic misaligned, BranchMisalignedFaultE, BranchMisalignedFaultM, TrapMisalignedFaultM; logic misaligned, BranchMisalignedFaultE, BranchMisalignedFaultM, TrapMisalignedFaultM;
logic StallExceptResolveBranchesF, PrivilegedChangePCM; logic StallExceptResolveBranchesF, PrivilegedChangePCM;
logic [`XLEN-3:0] PCPlusUpperF; logic [`XLEN-3:0] PCPlusUpperF;
@ -52,7 +49,7 @@ module pclogic #(parameter PCSTART) (
assign PCTargetE = ExtImmE + TargetBaseE; assign PCTargetE = ExtImmE + TargetBaseE;
mux3 #(`XLEN) pcmux(PCPlus2or4F, PCTargetE, PrivilegedNextPCM, {PrivilegedChangePCM, PCSrcE}, UnalignedPCNextF); mux3 #(`XLEN) pcmux(PCPlus2or4F, PCTargetE, PrivilegedNextPCM, {PrivilegedChangePCM, PCSrcE}, UnalignedPCNextF);
assign PCNextF = {UnalignedPCNextF[`XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment assign PCNextF = {UnalignedPCNextF[`XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment
flopenl #(`XLEN) pcreg(clk, reset, ~StallExceptResolveBranchesF, PCNextF, ResetVector, PCF); flopenl #(`XLEN) pcreg(clk, reset, ~StallExceptResolveBranchesF, PCNextF, `RESET_VECTOR, PCF);
// pcadder // pcadder
// add 2 or 4 to the PC, based on whether the instruction is 16 bits or 32 // add 2 or 4 to the PC, based on whether the instruction is 16 bits or 32

4
wally-pipelined/src/wallypipelinedhart.sv
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@ -25,7 +25,7 @@
`include "wally-config.vh" `include "wally-config.vh"
module wallypipelinedhart #(parameter PCSTART = 32'h80000000) ( module wallypipelinedhart (
input logic clk, reset, input logic clk, reset,
output logic [`XLEN-1:0] PCF, output logic [`XLEN-1:0] PCF,
input logic [31:0] InstrF, input logic [31:0] InstrF,
@ -70,7 +70,7 @@ module wallypipelinedhart #(parameter PCSTART = 32'h80000000) (
logic FloatRegWriteW; logic FloatRegWriteW;
controller c(.*); controller c(.*);
datapath #(PCSTART) dp(.*); datapath dp(.*);
hazard hz(.*); hazard hz(.*);
// add FPU here, with SetFflagsM, FRM_REGW // add FPU here, with SetFflagsM, FRM_REGW