From b76941d278890d91c96e4a5e21619f9a6ddd30c3 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 21 Jun 2024 15:17:59 -0700 Subject: [PATCH] Use VCS built-in default macro instead of defining SIM_VCS --- sim/vcs/run_vcs | 2 +- testbench/testbench.sv | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/sim/vcs/run_vcs b/sim/vcs/run_vcs index 5601e57b2..80385f6ba 100755 --- a/sim/vcs/run_vcs +++ b/sim/vcs/run_vcs @@ -90,7 +90,7 @@ RTL_FILES="$INCLUDE_DIRS $(find ${SRC} -name "*.sv" ! -path "${SRC}/generic/mem/ # Simulation and Coverage Commands OUTPUT="sim_out" -VCS_CMD="vcs +lint=all,noGCWM,noUI,noSVA-UA,noIDTS,noNS,noULCO,noCAWM-L,noWMIA-L,noSV-PIU,noSTASKW_CO,noSTASKW_CO1,noSTASKW_RMCOF +vcs+vcdpluson -suppress +warn -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse -ntb_opts sensitive_dyn +define+SIM_VCS ${INCLUDE_PATH} $RTL_FILES" +VCS_CMD="vcs +lint=all,noGCWM,noUI,noSVA-UA,noIDTS,noNS,noULCO,noCAWM-L,noWMIA-L,noSV-PIU,noSTASKW_CO,noSTASKW_CO1,noSTASKW_RMCOF +vcs+vcdpluson -suppress +warn -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse -ntb_opts sensitive_dyn ${INCLUDE_PATH} $RTL_FILES" SIMV_CMD="./${WKDIR}/$OUTPUT +TEST=${TESTSUITE} ${PLUSARGS}" COV_FILES="${TB}/coverage/test_pmp_coverage.sv" COV_OPTIONS="-cm line+cond+branch+fsm+tgl -cm_log ${WKDIR}/coverage.log -cm_dir ${WKDIR}/COVERAGE" diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 9f2b42a5a..8cd10f083 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -54,7 +54,7 @@ module testbench; `ifdef VERILATOR import "DPI-C" function string getenvval(input string env_name); string RISCV_DIR = getenvval("RISCV"); // "/opt/riscv"; - `elsif SIM_VCS + `elsif VCS import "DPI-C" function string getenv(input string env_name); string RISCV_DIR = getenv("RISCV"); // "/opt/riscv"; `else @@ -421,7 +421,7 @@ module testbench; $display("Single Elf file tests are not signatured verified."); `ifdef VERILATOR // this macro is defined when verilator is used $finish; // Simulator Verilator needs $finish to terminate simulation. -`elsif SIM_VCS // this macro is defined when vcs is used +`elsif VCS // this macro is defined when vcs is used $finish; // Simulator VCS needs $finish to terminate simulation. `else $stop; // if this is changed to $finish for Questa, wally-batch.do does not go to the next step to run coverage, and wally.do terminates without allowing GUI debug @@ -442,7 +442,7 @@ module testbench; else $display("FAIL: %d test programs had errors", totalerrors); `ifdef VERILATOR // this macro is defined when verilator is used $finish; // Simulator Verilator needs $finish to terminate simulation. -`elsif SIM_VCS // this macro is defined when vcs is used +`elsif VCS // this macro is defined when vcs is used $finish; // Simulator VCS needs $finish to terminate simulation. `else $stop; // if this is changed to $finish for Questa, wally-batch.do does not go to the next step to run coverage, and wally.do terminates without allowing GUI debug