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removed reminant changes

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This commit is contained in:
Shreya Sanghai 2022-03-07 17:36:05 +00:00
parent b6b4d0f982
commit b73f81548f
1 changed files with 2 additions and 2 deletions
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4
synthDC/scripts/synth.tcl
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@ -22,7 +22,7 @@ set cfg "${hdl_src}/../config/${cfgName}/wally-config.vh"
set saifpower $::env(SAIFPOWER) set saifpower $::env(SAIFPOWER)
set maxopt $::env(MAXOPT) set maxopt $::env(MAXOPT)
# eval file copy -force ${cfg} {hdl/} eval file copy -force ${cfg} {hdl/}
eval file copy -force ${cfg} $outputDir eval file copy -force ${cfg} $outputDir
eval file copy -force [glob ${hdl_src}/../config/shared/*.vh] {hdl/} eval file copy -force [glob ${hdl_src}/../config/shared/*.vh] {hdl/}
eval file copy -force [glob ${hdl_src}/*/*.sv] {hdl/} eval file copy -force [glob ${hdl_src}/*/*.sv] {hdl/}
@ -34,7 +34,7 @@ if { $saifpower == 1 } {
} }
# Verilog files # Verilog files
set my_verilog_files [glob hdl/* outputDir/wally-config.vh] set my_verilog_files [glob hdl/*]
# Set toplevel # Set toplevel
set my_toplevel $::env(DESIGN) set my_toplevel $::env(DESIGN)