diff --git a/pipelined/src/lsu/busfsm.sv b/pipelined/src/lsu/busfsm.sv
index fbe660e81..04fb6d9af 100644
--- a/pipelined/src/lsu/busfsm.sv
+++ b/pipelined/src/lsu/busfsm.sv
@@ -40,17 +40,15 @@ module busfsm #(parameter integer LOGWPL)
    input logic               BusAck,
    input logic               BusInit, // This might be better as LSUBusLock, or to send this using BusAck.
    input logic               CPUBusy,
-   input logic               Cacheable,
 
    output logic              BusStall,
    output logic              BusWrite,
    output logic              SelBusWord,
    output logic              BusRead,
-   output logic [2:0]        HBURST,
    output logic              BusTransComplete,
    output logic [1:0]        HTRANS,
-   output logic              BusCommitted,
-   output logic              BufferCaptureEn);
+   output logic              BusCommitted
+);
   
   typedef enum logic [2:0] {STATE_BUS_READY,
 				STATE_BUS_UNCACHED_WRITE,
@@ -87,22 +85,17 @@ module busfsm #(parameter integer LOGWPL)
 	endcase
   end
 
-  assign HBURST = 3'b0;
   assign BusTransComplete = BusAck;
-  // Use SEQ if not doing first word, NONSEQ if doing the first read/write, and IDLE if finishing up.
-  assign HTRANS = (BusRead | BusWrite) & (~BusTransComplete) ? AHB_NONSEQ : AHB_IDLE; 
-   
   assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & |RW) |
 					(BusCurrState == STATE_BUS_UNCACHED_WRITE) |
 					(BusCurrState == STATE_BUS_UNCACHED_READ);
   assign BusWrite = (BusCurrState == STATE_BUS_READY & RW[0] & ~IgnoreRequest) |
 							   (BusCurrState == STATE_BUS_UNCACHED_WRITE);
+  assign BusRead = (BusCurrState == STATE_BUS_READY & RW[1] & ~IgnoreRequest) |
+							  (BusCurrState == STATE_BUS_UNCACHED_READ);
+  assign BusCommitted = BusCurrState != STATE_BUS_READY;
   assign SelBusWord = (BusCurrState == STATE_BUS_READY & RW[0]) |
 						   (BusCurrState == STATE_BUS_UNCACHED_WRITE);
 
-  assign BusRead = (BusCurrState == STATE_BUS_READY & RW[1] & ~IgnoreRequest) |
-							  (BusCurrState == STATE_BUS_UNCACHED_READ);
-  assign BufferCaptureEn = BusRead;
-
-  assign BusCommitted = BusCurrState != STATE_BUS_READY;
+  assign HTRANS = (BusRead | BusWrite) & (~BusAck) ? AHB_NONSEQ : AHB_IDLE; 
 endmodule
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index 7c63cb533..51a29cf3b 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -251,19 +251,18 @@ module lsu (
       mux2 #(`XLEN) LSUHWDATAMux(.d0(ReadDataWordM[`XLEN-1:0]), .d1(LSUWriteDataM[`XLEN-1:0]),
         .s(SelUncachedAdr), .y(LSUHWDATA));
     end else begin : passthrough // just needs a register to hold the value from the bus
-      logic                BufferCaptureEn;
-
-      flopen #(`XLEN) fb(.clk, .en(BufferCaptureEn), .d(HRDATA), .q(ReadDataWordMuxM));
+      flopen #(`XLEN) fb(.clk, .en(LSUBusRead), .d(HRDATA), .q(ReadDataWordMuxM));
       assign LSUHWDATA = LSUWriteDataM[`XLEN-1:0];
 
       busfsm #(LOGBWPL) busfsm(
         .clk, .reset, .IgnoreRequest, .RW(LSURWM), 
-        .BusAck(LSUBusAck), .BusInit(LSUBusInit), .CPUBusy, .Cacheable(1'b0), .BusStall, .BusWrite(LSUBusWrite), 
-        .SelBusWord, .BusRead(LSUBusRead), .BufferCaptureEn,
-        .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .BusTransComplete(LSUTransComplete), 
+        .BusAck(LSUBusAck), .BusInit(LSUBusInit), .CPUBusy, .BusStall, .BusWrite(LSUBusWrite), 
+        .SelBusWord, .BusRead(LSUBusRead), 
+        .HTRANS(LSUHTRANS), .BusTransComplete(LSUTransComplete), 
         .BusCommitted(BusCommittedM));
     
       // *** possible bug - ReadDatWordM vs. ReadDataWordMuxW - is byte swapping needed for endian
+      assign LSUHBURST = 3'b0;
       assign {ReadDataWordM, DCacheStallM, DCacheCommittedM, DCacheFetchLine, DCacheWriteLine} = '0;
       assign DCacheMiss = CacheableM; assign DCacheAccess = CacheableM;
     end