From b723e16893ebfa9ad676e6585d0200099dff95f5 Mon Sep 17 00:00:00 2001
From: cturek <cturek@hmc.edu>
Date: Wed, 9 Nov 2022 18:41:26 +0000
Subject: [PATCH] Fixed asign and bsign

---
 pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
index 756c5cc9f..b3d81705c 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
@@ -67,8 +67,8 @@ module fdivsqrtpreproc (
   // ***can probably merge X LZC with conversion
   // cout the number of leading zeros
 
-  assign As = ForwardedSrcAE[`XLEN-1] & Funct3E[0];
-  assign Bs = ForwardedSrcBE[`XLEN-1] & Funct3E[0];
+  assign As = ForwardedSrcAE[`XLEN-1] & ~Funct3E[0];
+  assign Bs = ForwardedSrcBE[`XLEN-1] & ~Funct3E[0];
   assign A64 = W64E ? {{(`XLEN-32){As}}, ForwardedSrcAE[31:0]} : ForwardedSrcAE;
   assign B64 = W64E ? {{(`XLEN-32){Bs}}, ForwardedSrcBE[31:0]} : ForwardedSrcBE;