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Added mux to select between uncache instruction requests and cached instructions requests.

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Cacheless design almost works with the exception of compressed instructions.
This commit is contained in:
Ross Thompson 2021-12-30 18:09:37 -06:00
parent 58ef91c94b
commit b6fbc4a1e3
1 changed files with 10 additions and 3 deletions
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13
wally-pipelined/src/ifu/ifu.sv
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@ -91,7 +91,7 @@ module ifu (
logic [`XLEN-1:0] PCPlus2or4F, PCLinkD;
logic [`XLEN-3:0] PCPlusUpperF;
logic CompressedF;
logic [31:0] InstrRawD, FinalInstrRawF;
logic [31:0] InstrRawD, FinalInstrRawF, InstrRawF;
logic [31:0] InstrE;
logic [`XLEN-1:0] PCD;
@ -197,7 +197,7 @@ module ifu (
generate
if(`MEM_ICACHE) begin : icache
icache icache(.clk, .reset, .CPUBusy(StallF), .IgnoreRequest, .ICacheMemWriteData , .ICacheBusAck,
.ICacheBusAdr, .CompressedF, .ICacheStallF, .ITLBMissF, .ITLBWriteF, .FinalInstrRawF, // need mux to select between cached and uncached instr.
.ICacheBusAdr, .CompressedF, .ICacheStallF, .ITLBMissF, .ITLBWriteF, .FinalInstrRawF,
.ICacheFetchLine,
.CacheableF,
.PCNextF(PCNextFPhys),
@ -210,9 +210,16 @@ module ifu (
assign ICacheBusAdr = 0;
assign CompressedF = 0; //?
assign ICacheStallF = 0;
assign FinalInstrRawF = 0;
end
endgenerate
// select between dcache and direct from the BUS. Always selected if no dcache.
mux2 #(32) UnCachedInstrMux(.d0(FinalInstrRawF),
.d1(ICacheMemWriteData[31:0]),
.s(SelUncachedAdr),
.y(InstrRawF));
genvar index;
generate
@ -243,7 +250,7 @@ module ifu (
flopenl #(32) AlignedInstrRawDFlop(clk, reset | reset_q, ~StallD, FlushD ? nop : FinalInstrRawF, nop, InstrRawD);
flopenl #(32) AlignedInstrRawDFlop(clk, reset | reset_q, ~StallD, FlushD ? nop : InstrRawF, nop, InstrRawD);
assign PrivilegedChangePCM = RetM | TrapM;