Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

wally-pipelined/regression/wave.do

@@ -15,6 +15,8 @@ add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICa
 add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall
 add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
 add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/DivBusyE
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/trap/PendingInterruptM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/trap/InterruptM
 add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/BreakpointFaultM
 add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/DTLBLoadPageFaultM
 add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/DTLBStorePageFaultM
@@ -107,21 +109,21 @@ add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/if
 add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredClassNonCFIWrongE
 add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
 add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
-add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCNextF
+add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCNextF
-add wave -noupdate -expand -group PCS /testbench/dut/hart/PCF
+add wave -noupdate -group PCS /testbench/dut/hart/PCF
-add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCD
+add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCD
-add wave -noupdate -expand -group PCS /testbench/dut/hart/PCE
+add wave -noupdate -group PCS /testbench/dut/hart/PCE
-add wave -noupdate -expand -group PCS /testbench/dut/hart/PCM
+add wave -noupdate -group PCS /testbench/dut/hart/PCM
-add wave -noupdate -expand -group PCS /testbench/PCW
+add wave -noupdate -group PCS /testbench/PCW
-add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
-add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
-add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
+add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
-add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredPCF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredPCF
-add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext0F
+add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext0F
-add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F
+add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F
-add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF
-add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE
+add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE
-add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM
+add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM
 add wave -noupdate -group RegFile -expand /testbench/dut/hart/ieu/dp/regf/rf
 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
@@ -211,6 +213,8 @@ add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/ReadDataWordMuxM
 add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/ReadDataM
 add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WriteDataM
 add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/SelUncached
+add wave -noupdate -expand -group lsu -expand -group bus -color Gold /testbench/dut/hart/lsu/BusCurrState
+add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/BusStall
 add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState
 add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WayHit
 add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
@@ -228,7 +232,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group flush -radix
 add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/FlushWay
 add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimDirtyWay
 add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimTag
-add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/BasePAdrM
 add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/CacheableM
 add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WriteEnable}
@@ -333,7 +336,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group status /testb
 add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/DCFetchLine
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/DCWriteLine
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BasePAdrM
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BUSACK
 add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/FlushWay
@@ -376,16 +378,16 @@ add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pm
 add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/W
 add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/X
 add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/L
-add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/genblk1/WalkerState
+add wave -noupdate -expand -group lsu -group ptwalker -color Gold /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/genblk1/WalkerState
-add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/PCF
+add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/PCF
-add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/genblk1/TranslationVAdr
+add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/genblk1/TranslationVAdr
-add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWReadPTE
+add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWReadPTE
-add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWAdr
+add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWAdr
-add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/PTE
+add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/PTE
-add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/ITLBMissF
+add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/ITLBMissF
-add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/DTLBMissM
+add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/DTLBMissM
-add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/ITLBWriteF
+add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/ITLBWriteF
-add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/DTLBWriteM
+add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/DTLBWriteM
 add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
 add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
 add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
@@ -464,9 +466,13 @@ add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW
 add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PCNext2F
 add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PrivilegedNextPCM
 add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PrivilegedChangePCM
+add wave -noupdate /testbench/dut/hart/priv/priv/csr/MEPC_REGW
+add wave -noupdate /testbench/dut/hart/lsu/LocalLsuBusAdr
+add wave -noupdate /testbench/dut/hart/lsu/BasePAdrMaskedM
+add wave -noupdate /testbench/dut/hart/lsu/match
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 7} {31851 ns} 1} {{Cursor 5} {207375 ns} 0}
+WaveRestoreCursors {{Cursor 7} {36865 ns} 1} {{Cursor 5} {49445 ns} 1} {{Cursor 3} {35021 ns} 0} {{Cursor 4} {49574 ns} 1}
-quietly wave cursor active 2
+quietly wave cursor active 3
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 314
 configure wave -justifyvalue left
@@ -481,4 +487,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {207017 ns} {208185 ns}
+WaveRestoreZoom {34887 ns} {35269 ns}

wally-pipelined/src/cache/dcache.sv

@@ -44,13 +44,13 @@ module dcache
    output logic 							DCacheStall,
    output logic 							DCacheMiss,
    output logic 							DCacheAccess,
-
+   output logic 							DCCommittedM,
    output logic 							DCWriteLine,
    output logic 							DCFetchLine,
    input logic 								BUSACK,
    
 
-   output logic [`PA_BITS-1:0] 				BasePAdrM,
+   output logic [`PA_BITS-1:0] 				DCacheBusAdr,
    output logic [`XLEN-1:0] 				ReadDataBlockSetsM [(`DCACHE_BLOCKLENINBITS/`XLEN)-1:0],
 
    output logic 							SelFlush,
@@ -232,11 +232,11 @@ module dcache
 				.y(SRAMWriteData));
 
   
-  mux3 #(`PA_BITS) BaseAdrMux(.d0(MemPAdrM),
+  mux3 #(`PA_BITS) BaseAdrMux(.d0({MemPAdrM[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
 			      .d1({VictimTag, MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
 			      .d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}),
 			      .s({SelFlush, SelEvict}),
-			      .y(BasePAdrM));
+			      .y(DCacheBusAdr));
 
 
   // flush address and way generation.
@@ -281,6 +281,7 @@ module dcache
  		      .CacheHit,
  		      .VictimDirty,
 		      .DCacheStall,
+					 .DCCommittedM, 
 		      .DCacheMiss,
 		      .DCacheAccess,
 		      .SelAdrM,

wally-pipelined/src/cache/dcachefsm.sv

@@ -50,7 +50,7 @@ module dcachefsm
    output logic 	  DCacheMiss,
    output logic 	  DCacheAccess,
    // Bus outputs
-
+   output logic       DCCommittedM,
    output logic 	  DCWriteLine,
    output logic 	  DCFetchLine,
 
@@ -391,7 +391,7 @@ module dcachefsm
     endcase
   end
 
-
+  assign DCCommittedM = CurrState != STATE_READY;
 
 endmodule // dcachefsm
 

wally-pipelined/src/lsu/lsu.sv

@@ -42,6 +42,7 @@ module lsu
    input logic 				   ExceptionM,
    input logic 				   PendingInterruptM,
    input logic 				   FlushDCacheM,
+   output logic 			   CommittedM, 
    output logic 			   SquashSCW,
    output logic 			   DCacheMiss,
    output logic 			   DCacheAccess,
@@ -98,7 +99,7 @@ module lsu
   logic [1:0] 				   LsuRWM;
   logic [2:0] 				   LsuFunct3M;
   logic [1:0] 				   LsuAtomicM;
-  logic [`PA_BITS-1:0] 		   LsuPAdrM;
+  logic [`PA_BITS-1:0] 		   LsuPAdrM, LocalLsuBusAdr;
   logic [11:0] 				   LsuAdrE, DCAdrE;  
   logic 					   CPUBusy;
   logic 					   MemReadM;
@@ -114,6 +115,7 @@ module lsu
 
   logic 					   InterlockStall;
   logic 					   IgnoreRequest;
+  logic 					   BusCommittedM, DCCommittedM;
   
 
   flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
@@ -216,6 +218,7 @@ module lsu
 	  mux2 #(`PA_BITS) lsupadrmux(IEUAdrExtM[`PA_BITS-1:0], HPTWAdr, SelHPTW, LsuPAdrM);
 
 	  assign CPUBusy = StallW & ~SelHPTW;
+	  
 	  // always block interrupts when using the hardware page table walker.
 
 	  // this is for the d cache SRAM.
@@ -260,6 +263,7 @@ module lsu
 	end
   endgenerate
 
+  assign CommittedM = SelHPTW | DCCommittedM | BusCommittedM;
 
   mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
   dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
@@ -323,13 +327,12 @@ module lsu
   localparam integer   LOGWPL = $clog2(WORDSPERLINE);
   localparam integer   BLOCKLEN = `DCACHE_BLOCKLENINBITS;
   
-  localparam integer   FetchCountThreshold = WORDSPERLINE - 1;
+  localparam integer   WordCountThreshold = WORDSPERLINE - 1;
   localparam integer   BLOCKBYTELEN = BLOCKLEN/8;
   localparam integer   OFFSETLEN = $clog2(BLOCKBYTELEN);
 
   // temp
-  logic 		       SelUncached;
+  logic 			   WordCountFlag;
-  logic 			   FetchCountFlag;
   
   logic [`XLEN-1:0]    FinalAMOWriteDataM, FinalWriteDataM;
   (* mark_debug = "true" *) logic [`XLEN-1:0]    DC_HWDATA_FIXNAME;
@@ -341,13 +344,13 @@ module lsu
   logic [`XLEN-1:0]    ReadDataWordMuxM;
 
 
-  logic [LOGWPL-1:0]   FetchCount, NextFetchCount;
+  logic [LOGWPL-1:0]   WordCount, NextWordCount;
   logic [`PA_BITS-1:0] 	       BasePAdrMaskedM;  
   logic [OFFSETLEN-1:0]        BasePAdrOffsetM;
 
   logic 			   CntEn, PreCntEn;
   logic 			   CntReset;
-  logic [`PA_BITS-1:0] BasePAdrM;
+  logic [`PA_BITS-1:0] DCacheBusAdr;
   logic [`XLEN-1:0]    ReadDataBlockSetsM [(`DCACHE_BLOCKLENINBITS/`XLEN)-1:0];
   
 
@@ -356,6 +359,11 @@ module lsu
   logic 			   DCFetchLine;
   logic 			   BUSACK;
 
+  logic 			   UnCachedLsuBusRead;
+  logic 			   UnCachedLsuBusWrite;
+  logic 			   SelUncachedAdr;
+
+  
   dcache dcache(.clk, .reset, .CPUBusy,
 				.MemRWM(DCRWM),
 				.Funct3M(LsuFunct3M),
@@ -366,8 +374,8 @@ module lsu
 				.FinalWriteDataM, .ReadDataWordM, .DCacheStall,
 				.DCacheMiss, .DCacheAccess, .IgnoreRequest,
 				.CacheableM(CacheableM), 
-
+				.DCCommittedM,
-				.BasePAdrM,
+				.DCacheBusAdr,
 				.ReadDataBlockSetsM,
 				.SelFlush,
 				.DCacheMemWriteData,
@@ -379,7 +387,7 @@ module lsu
 
   mux2 #(`XLEN) UnCachedDataMux(.d0(ReadDataWordM),
 				.d1(DCacheMemWriteData[`XLEN-1:0]),
-				.s(SelUncached),
+				.s(SelUncachedAdr),
 				.y(ReadDataWordMuxM));
   
   // finally swr
@@ -407,8 +415,8 @@ module lsu
   assign LsuBusHWDATA = CacheableM | SelFlush ? DC_HWDATA_FIXNAME : WriteDataM;
 
   generate
-    if (`XLEN == 32) assign LsuBusSize = CacheableM | SelFlush ? 3'b010 : LsuFunct3M;
+    if (`XLEN == 32) assign LsuBusSize = UnCachedLsuBusWrite | UnCachedLsuBusRead ? LsuFunct3M : 3'b010;
-    else assign LsuBusSize = CacheableM | SelFlush ? 3'b011 : LsuFunct3M;
+    else assign LsuBusSize = UnCachedLsuBusWrite | UnCachedLsuBusRead ? LsuFunct3M : 3'b011;
   endgenerate;
 
   // Bus Side logic
@@ -420,33 +428,32 @@ module lsu
   generate
     for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer
       flopen #(`XLEN) fb(.clk(clk),
-			 .en(LsuBusAck & LsuBusRead & (index == FetchCount)),
+			 .en(LsuBusAck & LsuBusRead & (index == WordCount)),
 			 .d(LsuBusHRDATA),
 			 .q(DCacheMemWriteData[(index+1)*`XLEN-1:index*`XLEN]));
     end
   endgenerate
 
 
-  // if not cacheable the offset bits needs to be sent to the EBU.
-  // if cacheable the offset bits are discarded.  $ FSM will fetch the whole block.
-  assign BasePAdrOffsetM = CacheableM ? {{OFFSETLEN}{1'b0}} : BasePAdrM[OFFSETLEN-1:0];
-  assign BasePAdrMaskedM = {BasePAdrM[`PA_BITS-1:OFFSETLEN], BasePAdrOffsetM};
 
-  assign LsuBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, FetchCount} << $clog2(`XLEN/8)) + BasePAdrMaskedM;
+  //assign LocalLsuBusAdr = SelUncachedAdr ? MemPAdrM : {DCacheBusAdr[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}} ;
+  assign LocalLsuBusAdr = SelUncachedAdr ? MemPAdrM : DCacheBusAdr ;
 
-  assign DC_HWDATA_FIXNAME = ReadDataBlockSetsM[FetchCount];
+  assign LsuBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalLsuBusAdr;
   
-  assign FetchCountFlag = (FetchCount == FetchCountThreshold[LOGWPL-1:0]);
+  assign DC_HWDATA_FIXNAME = ReadDataBlockSetsM[WordCount];
+
+  assign WordCountFlag = (WordCount == WordCountThreshold[LOGWPL-1:0]);
   assign CntEn = PreCntEn & LsuBusAck;
 
   flopenr #(LOGWPL) 
-  FetchCountReg(.clk(clk),
+  WordCountReg(.clk(clk),
 		.reset(reset | CntReset),
 		.en(CntEn),
-		.d(NextFetchCount),
+		.d(NextWordCount),
-		.q(FetchCount));
+		.q(WordCount));
 
-  assign NextFetchCount = FetchCount + 1'b1;
+  assign NextWordCount = WordCount + 1'b1;
 
   typedef enum {STATE_BUS_READY,
 				STATE_BUS_FETCH,
@@ -454,7 +461,8 @@ module lsu
 				STATE_BUS_UNCACHED_WRITE,
 				STATE_BUS_UNCACHED_WRITE_DONE,
 				STATE_BUS_UNCACHED_READ,
-				STATE_BUS_UNCACHED_READ_DONE} busstatetype;
+				STATE_BUS_UNCACHED_READ_DONE,
+				STATE_BUS_CPU_BUSY} busstatetype;
 
   (* mark_debug = "true" *) busstatetype BusCurrState, BusNextState;
 
@@ -464,101 +472,54 @@ module lsu
   
   always_comb begin
 	BusNextState = STATE_BUS_READY;
-	CntReset = 1'b0;
-	BusStall = 1'b0;
-	PreCntEn = 1'b0;
-	LsuBusWrite = 1'b0;
-	LsuBusRead = 1'b0;
-	BUSACK = 1'b0;
-	SelUncached = 1'b0;
 	
 	case(BusCurrState)
-	  STATE_BUS_READY: begin
+	  STATE_BUS_READY:           if(IgnoreRequest)               BusNextState = STATE_BUS_READY;
-		if(IgnoreRequest) begin
+	                             else if(DCRWM[0] & ~CacheableM) BusNextState = STATE_BUS_UNCACHED_WRITE;
-		  BusNextState = STATE_BUS_READY;
+		                         else if(DCRWM[1] & ~CacheableM) BusNextState = STATE_BUS_UNCACHED_READ;
-		end else
+		                         else if(DCFetchLine)            BusNextState = STATE_BUS_FETCH;
-		// uncache write
+		                         else if(DCWriteLine)            BusNextState = STATE_BUS_WRITE;
-		if(DCRWM[0] & ~CacheableM) begin
+      STATE_BUS_UNCACHED_WRITE:  if(LsuBusAck)                   BusNextState = STATE_BUS_UNCACHED_WRITE_DONE;
-		  BusNextState = STATE_BUS_UNCACHED_WRITE;
+		                         else                            BusNextState = STATE_BUS_UNCACHED_WRITE;
-		  CntReset = 1'b1;
+      STATE_BUS_UNCACHED_READ:   if(LsuBusAck)                   BusNextState = STATE_BUS_UNCACHED_READ_DONE;
-		  BusStall = 1'b1;
+		                         else                            BusNextState = STATE_BUS_UNCACHED_READ;
-		  LsuBusWrite = 1'b1;
+      STATE_BUS_UNCACHED_WRITE_DONE: if(CPUBusy)                 BusNextState = STATE_BUS_CPU_BUSY;
-		end
+                                     else                        BusNextState = STATE_BUS_READY;
-		// uncached read
+      STATE_BUS_UNCACHED_READ_DONE:  if(CPUBusy)                 BusNextState = STATE_BUS_CPU_BUSY;
-		else if(DCRWM[1] & ~CacheableM) begin
+                                     else                        BusNextState = STATE_BUS_READY;
-		  BusNextState = STATE_BUS_UNCACHED_READ;
+	  STATE_BUS_CPU_BUSY:            if(CPUBusy)                 BusNextState = STATE_BUS_CPU_BUSY;
-		  CntReset = 1'b1;
+                                     else                            BusNextState = STATE_BUS_READY;
-		  BusStall = 1'b1;
+      STATE_BUS_FETCH:           if (WordCountFlag & LsuBusAck)  BusNextState = STATE_BUS_READY;
-		  LsuBusRead = 1'b1;
+	                             else                            BusNextState = STATE_BUS_FETCH;
-		end
+      STATE_BUS_WRITE:           if(WordCountFlag & LsuBusAck)   BusNextState = STATE_BUS_READY;
-		// D$ Fetch Line
+	                             else                            BusNextState = STATE_BUS_WRITE;
-		else if(DCFetchLine) begin
-		  BusNextState = STATE_BUS_FETCH;
-		  CntReset = 1'b1;
-		  BusStall = 1'b1;
-		end
-		// D$ Write Line
-		else if(DCWriteLine) begin
-		  BusNextState = STATE_BUS_WRITE;
-		  CntReset = 1'b1;
-		  BusStall = 1'b1;
-		end
-	  end
-
-      STATE_BUS_UNCACHED_WRITE : begin
-		BusStall = 1'b1;	
-		LsuBusWrite = 1'b1;
-		if(LsuBusAck) begin
-		  BusNextState = STATE_BUS_UNCACHED_WRITE_DONE;
-		end else begin
-		  BusNextState = STATE_BUS_UNCACHED_WRITE;
-		end
-      end
-
-      STATE_BUS_UNCACHED_READ: begin
-		BusStall = 1'b1;	
-		LsuBusRead = 1'b1;
-		if(LsuBusAck) begin
-		  BusNextState = STATE_BUS_UNCACHED_READ_DONE;
-		end else begin
-		  BusNextState = STATE_BUS_UNCACHED_READ;
-		end
-      end
-      
-      STATE_BUS_UNCACHED_WRITE_DONE: begin
-		BusNextState = STATE_BUS_READY;
-      end
-
-      STATE_BUS_UNCACHED_READ_DONE: begin
-		SelUncached = 1'b1;
-      end
-
-      STATE_BUS_FETCH: begin
-		BusStall = 1'b1;
-        PreCntEn = 1'b1;
-		LsuBusRead = 1'b1;
-		
-        if (FetchCountFlag & LsuBusAck) begin
-          BusNextState = STATE_BUS_READY;
-		  BUSACK = 1'b1;
-        end else begin
-          BusNextState = STATE_BUS_FETCH;
-        end
-      end
-
-      STATE_BUS_WRITE: begin
-		BusStall = 1'b1;
-        PreCntEn = 1'b1;
-		LsuBusWrite = 1'b1;
-		if(FetchCountFlag & LsuBusAck) begin
-		  BusNextState = STATE_BUS_READY;
-		  BUSACK = 1'b1;
-		end else begin
-		  BusNextState = STATE_BUS_WRITE;
-		end	  
-      end
 	endcase
   end
 
+
+  assign CntReset = BusCurrState == STATE_BUS_READY;
+  assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((~CacheableM & (|DCRWM)) | DCFetchLine | DCWriteLine)) |
+					(BusCurrState == STATE_BUS_UNCACHED_WRITE) |
+					(BusCurrState == STATE_BUS_UNCACHED_READ) |
+					(BusCurrState == STATE_BUS_FETCH)  |
+					(BusCurrState == STATE_BUS_WRITE);
+  assign PreCntEn = BusCurrState == STATE_BUS_FETCH | BusCurrState == STATE_BUS_WRITE;
+  assign UnCachedLsuBusWrite = (BusCurrState == STATE_BUS_READY & ~CacheableM & (DCRWM[0])) |
+							   (BusCurrState == STATE_BUS_UNCACHED_WRITE);
+  assign LsuBusWrite = UnCachedLsuBusWrite | (BusCurrState == STATE_BUS_WRITE);
+
+  assign UnCachedLsuBusRead = (BusCurrState == STATE_BUS_READY & ~CacheableM & (|DCRWM[1])) |
+							  (BusCurrState == STATE_BUS_UNCACHED_READ);
+  assign LsuBusRead = UnCachedLsuBusRead | (BusCurrState == STATE_BUS_FETCH);
+
+  assign BUSACK = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & LsuBusAck) |
+				  (BusCurrState == STATE_BUS_WRITE & WordCountFlag & LsuBusAck);
+  assign BusCommittedM = BusCurrState != STATE_BUS_READY;
+  assign SelUncachedAdr = (BusCurrState == STATE_BUS_READY & (|DCRWM & ~CacheableM)) |
+						  (BusCurrState == STATE_BUS_UNCACHED_READ |
+						   BusCurrState == STATE_BUS_UNCACHED_READ_DONE |
+						   BusCurrState == STATE_BUS_UNCACHED_WRITE |
+						   BusCurrState == STATE_BUS_UNCACHED_WRITE_DONE);
+    
 endmodule
 

wally-pipelined/src/privileged/privileged.sv

@@ -39,7 +39,7 @@ module privileged (
   output logic [`XLEN-1:0] PrivilegedNextPCM,
   output logic             RetM, TrapM, 
   output logic             ITLBFlushF, DTLBFlushM,
-  input  logic             InstrValidM, LSUStall,
+  input  logic             InstrValidM, CommittedM,
   input  logic             FRegWriteM, LoadStallD,
   input  logic 		   BPPredDirWrongM,
   input  logic 		   BTBPredPCWrongM,
@@ -230,7 +230,7 @@ module privileged (
             .PCM,
             .InstrMisalignedAdrM, .IEUAdrM, 
             .InstrM,
-            .InstrValidM, .LSUStall,
+            .InstrValidM, .CommittedM,
             .TrapM, .MTrapM, .STrapM, .UTrapM, .RetM,
             .InterruptM,
             .ExceptionM,

wally-pipelined/src/privileged/trap.sv

@@ -41,7 +41,7 @@ module trap (
   input logic [`XLEN-1:0]  PCM,
   input logic [`XLEN-1:0]  InstrMisalignedAdrM, IEUAdrM, 
   input logic [31:0] 	   InstrM,
-  input logic 		   InstrValidM, LSUStall,
+  input logic 		   InstrValidM, CommittedM,
   output logic 		   TrapM, MTrapM, STrapM, UTrapM, RetM,
   output logic 		   InterruptM,
   output logic 		   ExceptionM,
@@ -61,12 +61,12 @@ module trap (
   // Determine pending enabled interrupts
   // interrupt if any sources are pending
   // & with a M stage valid bit to avoid interrupts from interrupt a nonexistent flushed instruction (in the M stage)
-  // & with ~LSUStall to make sure MEPC isn't chosen so as to rerun the same instr twice
+  // & with ~CommittedM to make sure MEPC isn't chosen so as to rerun the same instr twice
   assign MIntGlobalEnM = (PrivilegeModeW != `M_MODE) || STATUS_MIE; // if M ints enabled or lower priv 3.1.9
   assign SIntGlobalEnM = (PrivilegeModeW == `U_MODE) || ((PrivilegeModeW == `S_MODE) && STATUS_SIE); // if in lower priv mode, or if S ints enabled and not in higher priv mode 3.1.9
   assign PendingIntsM = ((MIP_REGW & MIE_REGW) & ({12{MIntGlobalEnM}} & 12'h888)) | ((SIP_REGW & SIE_REGW) & ({12{SIntGlobalEnM}} & 12'h222));
   assign PendingInterruptM = (|PendingIntsM) & InstrValidM;  
-  assign InterruptM = PendingInterruptM & ~LSUStall; // previously CommittedM.  The purpose is to delay an interrupt if the instruction in the memory stage is busy in the LSU.  LSUStall directly provides this.
+  assign InterruptM = PendingInterruptM & ~CommittedM; 
   //assign ExceptionM = TrapM;
   assign ExceptionM = Exception1M;
   // *** as of 7/17/21, the system passes with this definition of ExceptionM as being all traps and fails if ExceptionM = Exception1M

wally-pipelined/src/wally/wallypipelinedhart.sv

@@ -125,6 +125,7 @@ module wallypipelinedhart (
   (* mark_debug = "true" *) logic [`XLEN-1:0] 	    IEUAdrM;  
   (* mark_debug = "true" *) logic [`XLEN-1:0] 	    ReadDataM;
   logic [`XLEN-1:0] 	    ReadDataW;  
+  logic 		    CommittedM;
 
   // AHB ifu interface
   logic [`PA_BITS-1:0] 	    InstrPAdrF;
@@ -239,7 +240,7 @@ module wallypipelinedhart (
 	// CPU interface
 	.MemRWM, .Funct3M, .Funct7M(InstrM[31:25]),
 	.AtomicM, .ExceptionM, .PendingInterruptM,		
-	.DCacheMiss, .DCacheAccess,
+	.CommittedM, .DCacheMiss, .DCacheAccess,
 	.SquashSCW,            
 	//.DataMisalignedM(DataMisalignedM),
 	.IEUAdrE, .IEUAdrM, .WriteDataM,
@@ -313,7 +314,7 @@ module wallypipelinedhart (
             .InstrM, .CSRReadValW, .PrivilegedNextPCM,
             .RetM, .TrapM, 
             .ITLBFlushF, .DTLBFlushM,
-            .InstrValidM, .LSUStall,
+            .InstrValidM, .CommittedM,
             .FRegWriteM, .LoadStallD,
             .BPPredDirWrongM, .BTBPredPCWrongM,
             .RASPredPCWrongM, .BPPredClassNonCFIWrongM,