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Modified LSU verilog is compatible with vivado. have to use extra logic IEUAdrExtM.

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This commit is contained in:
Ross Thompson 2021-12-20 10:03:56 -06:00
parent beb1988539
commit b6d75d453a
1 changed files with 3 additions and 1 deletions
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wally-pipelined/src/lsu/lsu.sv
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@ -94,6 +94,7 @@ module lsu
logic DTLBPageFaultM; logic DTLBPageFaultM;
logic [`PA_BITS-1:0] MemPAdrM; // from mmu to dcache logic [`PA_BITS-1:0] MemPAdrM; // from mmu to dcache
logic [`XLEN+1:0] IEUAdrExtM;
logic DTLBMissM; logic DTLBMissM;
logic DTLBWriteM; logic DTLBWriteM;
logic HPTWStall; logic HPTWStall;
@ -230,7 +231,8 @@ module lsu
//flop #(`PA_BITS) HPTWAdrMReg(clk, HPTWAdr, HPTWAdrM); // delay HPTWAdrM by a cycle //flop #(`PA_BITS) HPTWAdrMReg(clk, HPTWAdr, HPTWAdrM); // delay HPTWAdrM by a cycle
assign AtomicMtoDCache = SelHPTW ? 2'b00 : AtomicM; assign AtomicMtoDCache = SelHPTW ? 2'b00 : AtomicM;
assign MemPAdrNoTranslate = SelHPTW ? HPTWAdr : {2'b00, IEUAdrM}[`PA_BITS-1:0]; assign IEUAdrExtM = {2'b00, IEUAdrM};
assign MemPAdrNoTranslate = SelHPTW ? HPTWAdr : IEUAdrExtM[`PA_BITS-1:0];
assign MemAdrE = SelHPTW ? HPTWAdr[11:0] : IEUAdrE[11:0]; assign MemAdrE = SelHPTW ? HPTWAdr[11:0] : IEUAdrE[11:0];
assign CPUBusy = SelHPTW ? 1'b0 : StallW; assign CPUBusy = SelHPTW ? 1'b0 : StallW;
// always block interrupts when using the hardware page table walker. // always block interrupts when using the hardware page table walker.