Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Separated the icache from the bus fetching logic. I was able to share the same fsm between the lsu and ifu.

Browse Source
This commit is contained in:
Ross Thompson 2021-12-30 14:56:17 -06:00
parent 86514a6a23
commit b6c9d01f8b
5 changed files with 39 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

51
wally-pipelined/regression/wave.do
View File

@ -434,33 +434,36 @@ add wave -noupdate /testbench/dut/hart/lsu/busfsm/BusNextState
add wave -noupdate /testbench/dut/hart/lsu/busfsm/DCacheFetchLine add wave -noupdate /testbench/dut/hart/lsu/busfsm/DCacheFetchLine
add wave -noupdate /testbench/dut/hart/lsu/busfsm/DCacheWriteLine add wave -noupdate /testbench/dut/hart/lsu/busfsm/DCacheWriteLine
add wave -noupdate -expand -group ifu -color Gold /testbench/dut/hart/ifu/busfm/BusCurrState add wave -noupdate -expand -group ifu -color Gold /testbench/dut/hart/ifu/busfm/BusCurrState
add wave -noupdate -expand -group ifu -group icache -color Gold /testbench/dut/hart/ifu/icache/controller/CurrState add wave -noupdate -expand -group ifu /testbench/dut/hart/ifu/busfm/LsuBusAck
add wave -noupdate -expand -group ifu -group icache /testbench/dut/hart/ifu/icache/controller/NextState add wave -noupdate -expand -group ifu -expand -group icache -color Gold /testbench/dut/hart/ifu/icache/controller/CurrState
add wave -noupdate -expand -group ifu -group icache /testbench/dut/hart/ifu/ITLBMissF add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/controller/NextState
add wave -noupdate -expand -group ifu -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/ITLBMissF
add wave -noupdate -expand -group ifu -group icache /testbench/dut/hart/ifu/icache/ReadLineF add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF
add wave -noupdate -expand -group ifu -group icache /testbench/dut/hart/ifu/icache/SelAdr add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/ReadLineF
add wave -noupdate -expand -group ifu -group icache /testbench/dut/hart/ifu/icache/PCNextF add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/SelAdr
add wave -noupdate -expand -group ifu -group icache /testbench/dut/hart/ifu/icache/PCPF add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/PCNextF
add wave -noupdate -expand -group ifu -group icache /testbench/dut/hart/ifu/icache/PCPSpillF add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/PCPF
add wave -noupdate -expand -group ifu -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/PCPSpillF
add wave -noupdate -expand -group ifu -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
add wave -noupdate -expand -group ifu -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
add wave -noupdate -expand -group ifu -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
add wave -noupdate -expand -group ifu -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
add wave -noupdate -expand -group ifu -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
add wave -noupdate -expand -group ifu -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/FinalInstrRawF add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
add wave -noupdate -expand -group ifu -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheBusAdr add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/FinalInstrRawF
add wave -noupdate -expand -group ifu -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheBusAck add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheBusAdr
add wave -noupdate -expand -group ifu -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheBusAck
add wave -noupdate -expand -group ifu -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheMemWriteData add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
add wave -noupdate -expand -group ifu -group icache /testbench/dut/hart/ifu/icache/ICacheMemReadData add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheMemWriteData
add wave -noupdate -expand -group ifu -group icache /testbench/dut/hart/ifu/icache/SpillDataBlock0 add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/ICacheMemReadData
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/SpillDataBlock0
add wave -noupdate -expand -group ifu -group itlb /testbench/dut/hart/ifu/immu/TLBWrite add wave -noupdate -expand -group ifu -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
add wave -noupdate -expand -group ifu -group itlb /testbench/dut/hart/ifu/ITLBMissF add wave -noupdate -expand -group ifu -group itlb /testbench/dut/hart/ifu/ITLBMissF
add wave -noupdate -expand -group ifu -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress add wave -noupdate -expand -group ifu -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
add wave -noupdate /testbench/dut/hart/ifu/IfuBusRead
add wave -noupdate /testbench/dut/hart/ifu/icache/ICacheFetchLine
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 7} {36865 ns} 1} {{Cursor 5} {49445 ns} 1} {{Cursor 3} {0 ns} 0} {{Cursor 4} {49574 ns} 1} WaveRestoreCursors {{Cursor 7} {36865 ns} 1} {{Cursor 5} {49445 ns} 1} {{Cursor 3} {1239086 ns} 0} {{Cursor 4} {49574 ns} 1}
quietly wave cursor active 3 quietly wave cursor active 3
configure wave -namecolwidth 250 configure wave -namecolwidth 250
configure wave -valuecolwidth 314 configure wave -valuecolwidth 314
@ -476,4 +479,4 @@ configure wave -griddelta 40
configure wave -timeline 0 configure wave -timeline 0
configure wave -timelineunits ns configure wave -timelineunits ns
update update
WaveRestoreZoom {0 ns} {752 ns} WaveRestoreZoom {1238897 ns} {1239273 ns}

1
wally-pipelined/src/cache/icache.sv vendored
View File

@ -225,6 +225,7 @@ module icache
.IgnoreRequest, .IgnoreRequest,
.ICacheBusAck, .ICacheBusAck,
.ICacheFetchLine, .ICacheFetchLine,
.CacheableF,
.hit, .hit,
.spill, .spill,
.spillSave, .spillSave,

9
wally-pipelined/src/cache/icachefsm.sv vendored
View File

@ -36,6 +36,7 @@ module icachefsm
input logic ITLBWriteF, input logic ITLBWriteF,
input logic IgnoreRequest, input logic IgnoreRequest,
input logic CacheableF,
// BUS interface // BUS interface
input logic ICacheBusAck, input logic ICacheBusAck,
@ -132,7 +133,7 @@ module icachefsm
SelAdr = 2'b01; SelAdr = 2'b01;
ICacheStallF = 1'b0; ICacheStallF = 1'b0;
end end
else if (hit & ~spill) begin else if (CacheableF & hit & ~spill) begin
ICacheStallF = 1'b0; ICacheStallF = 1'b0;
LRUWriteEn = 1'b1; LRUWriteEn = 1'b1;
if(CPUBusy) begin if(CPUBusy) begin
@ -141,15 +142,15 @@ module icachefsm
end else begin end else begin
NextState = STATE_READY; NextState = STATE_READY;
end end
end else if (hit & spill) begin end else if (CacheableF & hit & spill) begin
spillSave = 1'b1; spillSave = 1'b1;
SelAdr = 2'b10; SelAdr = 2'b10;
LRUWriteEn = 1'b1; LRUWriteEn = 1'b1;
NextState = STATE_HIT_SPILL; NextState = STATE_HIT_SPILL;
end else if (~hit & ~spill) begin end else if (CacheableF & ~hit & ~spill) begin
SelAdr = 2'b01; /// *********( SelAdr = 2'b01; /// *********(
NextState = STATE_MISS_FETCH_WDV; NextState = STATE_MISS_FETCH_WDV;
end else if (~hit & spill) begin end else if (CacheableF & ~hit & spill) begin
SelAdr = 2'b01; SelAdr = 2'b01;
NextState = STATE_MISS_SPILL_FETCH_WDV; NextState = STATE_MISS_SPILL_FETCH_WDV;
end else begin end else begin

6
wally-pipelined/src/ifu/ifu.sv
View File

@ -189,7 +189,11 @@ module ifu (
logic [`PA_BITS-1:0] ICacheBusAdr; logic [`PA_BITS-1:0] ICacheBusAdr;
logic SelUncachedAdr; logic SelUncachedAdr;
// *** bug: on spill the second memory request does not go through the mmu(skips tlb, pmp, and pma checkers)
// also it is possible to have any above fault on the spilled accesses.
// I think the solution is to move the spill logic into the ifu using the busfsm and ensuring
// the mmu sees the spilled address.
icache icache(.clk, .reset, .CPUBusy(StallF), .IgnoreRequest, .ICacheMemWriteData , .ICacheBusAck, icache icache(.clk, .reset, .CPUBusy(StallF), .IgnoreRequest, .ICacheMemWriteData , .ICacheBusAck,
.ICacheBusAdr, .CompressedF, .ICacheStallF, .ITLBMissF, .ITLBWriteF, .FinalInstrRawF, .ICacheBusAdr, .CompressedF, .ICacheStallF, .ITLBMissF, .ITLBWriteF, .FinalInstrRawF,

2
wally-pipelined/src/lsu/busfsm.sv
View File

@ -125,7 +125,7 @@ module busfsm #(parameter integer WordCountThreshold,
assign UnCachedLsuBusRead = (BusCurrState == STATE_BUS_READY & ~CacheableM & (|LsuRWM[1])) | assign UnCachedLsuBusRead = (BusCurrState == STATE_BUS_READY & ~CacheableM & (|LsuRWM[1])) |
(BusCurrState == STATE_BUS_UNCACHED_READ); (BusCurrState == STATE_BUS_UNCACHED_READ);
assign LsuBusRead = UnCachedLsuBusRead | (BusCurrState == STATE_BUS_FETCH); assign LsuBusRead = UnCachedLsuBusRead | (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_READY & DCacheFetchLine);
assign DCacheBusAck = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & LsuBusAck) | assign DCacheBusAck = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & LsuBusAck) |
(BusCurrState == STATE_BUS_WRITE & WordCountFlag & LsuBusAck); (BusCurrState == STATE_BUS_WRITE & WordCountFlag & LsuBusAck);