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https://github.com/openhwgroup/cvw
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Merge pull request #1104 from davidharrishmc/dev
Privileged functional coverage tests run in regression-wally --fcov
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commit
b6b1fc82ab
@ -301,7 +301,8 @@ def addLockstepTestsByDir(dir, config, sim, fcovMode):
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for dirpath, dirnames, filenames in os.walk(os.path.abspath(dir)):
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for dirpath, dirnames, filenames in os.walk(os.path.abspath(dir)):
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for file in filenames:
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for file in filenames:
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# fcov lockstep only runs on WALLY-COV-ALL.elf files; other lockstep runs on all files
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# fcov lockstep only runs on WALLY-COV-ALL.elf files; other lockstep runs on all files
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if (file.endswith(".elf") and fcovMode == 0 or file.endswith("ALL.elf") and fcovMode == 1):
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if ((file.endswith(".elf") and (fcovMode == 0 or "tests/priv" in dir)) or
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(file.endswith("ALL.elf") and fcovMode == 1)):
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fullfile = os.path.join(dirpath, file)
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fullfile = os.path.join(dirpath, file)
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fields = fullfile.rsplit('/', 3)
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fields = fullfile.rsplit('/', 3)
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if (fields[2] == "ref"):
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if (fields[2] == "ref"):
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@ -419,9 +420,11 @@ if (args.ccov): # only run RV64GC tests on Questa in code coverage mode
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addTests(tests64gc_nofp, coveragesim)
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addTests(tests64gc_nofp, coveragesim)
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if (args.fp):
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if (args.fp):
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addTests(tests64gc_fp, coveragesim)
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addTests(tests64gc_fp, coveragesim)
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elif (args.fcov): # only run RV64GC tests on Questa in lockstep in functional coverage mode
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elif (args.fcov): # run tests in lockstep in functional coverage mode
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addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv32/", "rv32gc", coveragesim, 1)
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addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv32/", "rv32gc", coveragesim, 1)
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addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv64/", "rv64gc", coveragesim, 1)
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addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv64/", "rv64gc", coveragesim, 1)
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addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/priv/rv32/", "rv32gc", coveragesim, 1)
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addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/priv/rv64/", "rv64gc", coveragesim, 1)
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#addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege/src/", "rv64gc", coveragesim, 0)
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#addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege/src/", "rv64gc", coveragesim, 0)
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else:
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else:
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@ -115,7 +115,7 @@ module clint_apb import cvw::*; #(parameter cvw_t P) (
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always_ff @(posedge PCLK)
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always_ff @(posedge PCLK)
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if (~PRESETn) begin
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if (~PRESETn) begin
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MSIP <= 1'b0;
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MSIP <= 1'b0;
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MTIMECMP <= '0;
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MTIMECMP <= 64'hFFFFFFFFFFFFFFFF; // Spec says MTIMECMP is not reset, but we reset to maximum value to prevent spurious timer interrupts
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end else if (memwrite) begin
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end else if (memwrite) begin
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if (entry == 16'h0000) MSIP <= PWDATA[0];
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if (entry == 16'h0000) MSIP <= PWDATA[0];
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if (entry == 16'h4000)
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if (entry == 16'h4000)
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