From b67792086c7ff80cc2308440dbfd7fd59fccfe91 Mon Sep 17 00:00:00 2001 From: Katherine Parry Date: Thu, 7 Jul 2022 16:41:26 -0700 Subject: [PATCH] moved unsused division code again --- addins/riscv-arch-test | 2 +- pipelined/src/fpu/convert_inputs.sv | 74 -- pipelined/src/fpu/convert_inputs_div.sv | 47 - pipelined/src/fpu/divconv.sv | 126 -- pipelined/src/fpu/divconv_pipe.sv | 198 ---- pipelined/src/fpu/exception_div.sv | 82 -- pipelined/src/fpu/fpdiv.sv | 132 --- pipelined/src/fpu/fpdiv_pipe.sv | 170 --- pipelined/src/fpu/fpudivsqrtrecur.sv | 74 -- pipelined/src/fpu/fpudivsqrtrecurcore.sv | 105 -- pipelined/src/fpu/fsm_fpdiv.sv | 537 --------- pipelined/src/fpu/fsm_fpdiv_pipe.sv | 1330 ---------------------- pipelined/src/fpu/lzd_denorm.sv | 171 --- pipelined/src/fpu/redundantmul.sv | 58 - pipelined/src/fpu/rounder_denorm.sv | 259 ----- pipelined/src/fpu/rounder_div.sv | 212 ---- pipelined/src/fpu/sbtm_a0.sv | 170 --- pipelined/src/fpu/sbtm_a1.sv | 170 --- pipelined/src/fpu/sbtm_a2.sv | 234 ---- pipelined/src/fpu/sbtm_a3.sv | 230 ---- pipelined/src/fpu/sbtm_div.sv | 62 - pipelined/src/fpu/sbtm_sqrt.sv | 68 -- pipelined/src/fpu/shifter_denorm.sv | 164 --- pipelined/srt/qsel4.dat | 1024 ----------------- pipelined/srt/qsel4.sv | 1048 ----------------- pipelined/srt/sim-srt4 | 2 - pipelined/srt/sim-srt4-batch | 1 - pipelined/srt/srt-radix4.do | 31 - pipelined/srt/testbench-radix4.sv | 122 -- 29 files changed, 1 insertion(+), 6902 deletions(-) delete mode 100755 pipelined/src/fpu/convert_inputs.sv delete mode 100755 pipelined/src/fpu/convert_inputs_div.sv delete mode 100755 pipelined/src/fpu/divconv.sv delete mode 100755 pipelined/src/fpu/divconv_pipe.sv delete mode 100755 pipelined/src/fpu/exception_div.sv delete mode 100755 pipelined/src/fpu/fpdiv.sv delete mode 100755 pipelined/src/fpu/fpdiv_pipe.sv delete mode 100644 pipelined/src/fpu/fpudivsqrtrecur.sv delete mode 100644 pipelined/src/fpu/fpudivsqrtrecurcore.sv delete mode 100755 pipelined/src/fpu/fsm_fpdiv.sv delete mode 100755 pipelined/src/fpu/fsm_fpdiv_pipe.sv delete mode 100755 pipelined/src/fpu/lzd_denorm.sv delete mode 100644 pipelined/src/fpu/redundantmul.sv delete mode 100755 pipelined/src/fpu/rounder_denorm.sv delete mode 100755 pipelined/src/fpu/rounder_div.sv delete mode 100644 pipelined/src/fpu/sbtm_a0.sv delete mode 100644 pipelined/src/fpu/sbtm_a1.sv delete mode 100755 pipelined/src/fpu/sbtm_a2.sv delete mode 100755 pipelined/src/fpu/sbtm_a3.sv delete mode 100644 pipelined/src/fpu/sbtm_div.sv delete mode 100644 pipelined/src/fpu/sbtm_sqrt.sv delete mode 100755 pipelined/src/fpu/shifter_denorm.sv delete mode 100644 pipelined/srt/qsel4.dat delete mode 100644 pipelined/srt/qsel4.sv delete mode 100755 pipelined/srt/sim-srt4 delete mode 100755 pipelined/srt/sim-srt4-batch delete mode 100644 pipelined/srt/srt-radix4.do delete mode 100644 pipelined/srt/testbench-radix4.sv diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index 307c77b26..be67c99bd 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit 307c77b26e070ae85ffea665ad9b642b40e33c86 +Subproject commit be67c99bd461742aa1c100bcc0732657faae2230 diff --git a/pipelined/src/fpu/convert_inputs.sv b/pipelined/src/fpu/convert_inputs.sv deleted file mode 100755 index aec1aa017..000000000 --- a/pipelined/src/fpu/convert_inputs.sv +++ /dev/null @@ -1,74 +0,0 @@ -/////////////////////////////////////////// -// -// Written: James Stine -// Modified: 8/1/2018 -// -// Purpose: Floating point divider/square root top unit (Goldschmidt) -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// MIT LICENSE -// Permission is hereby granted, free of charge, to any person obtaining a copy of this -// software and associated documentation files (the "Software"), to deal in the Software -// without restriction, including without limitation the rights to use, copy, modify, merge, -// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons -// to whom the Software is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or -// substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE -// OR OTHER DEALINGS IN THE SOFTWARE. -//////////////////////////////////////////////////////////////////////////////////////////////// - -module convert_inputs( - input [63:0] op1, // 1st input operand (A) - input [63:0] op2, // 2nd input operand (B) - input [2:0] op_type, // Function opcode - input P, // Result Precision (0 for double, 1 for single) - - output [63:0] Float1, // Converted 1st input operand - output [63:0] Float2 // Converted 2nd input operand -); - - wire conv_SP; // Convert from SP to DP - wire Zexp1; // One if the exponent of op1 is zero - wire Zexp2; // One if the exponent of op2 is zero - wire Oexp1; // One if the exponent of op1 is all ones - wire Oexp2; // One if the exponent of op2 is all ones - - // Convert from single precision to double precision if (op_type is 11X - // and P is 0) or (op_type is not 11X and P is one). - assign conv_SP = ~P; - - // Test if the input exponent is zero, because if it is then the - // exponent of the converted number should be zero. - assign Zexp1 = ~(|op1[30:23]); - assign Zexp2 = ~(|op2[30:23]); - assign Oexp1 = (&op1[30:23]); - assign Oexp2 = (&op2[30:23]); - - // Conditionally convert op1. Lower 29 bits are zero for single precision. - assign Float1[62:29] = conv_SP ? {op1[30], {3{(~op1[30]&~Zexp1)|Oexp1}}, op1[29:0]} - : op1[62:29]; - assign Float1[28:0] = op1[28:0] & {29{~conv_SP}}; - - // Conditionally convert op2. Lower 29 bits are zero for single precision. - assign Float2[62:29] = conv_SP ? {op2[30], {3{(~op2[30]&~Zexp2)|Oexp2}}, op2[29:0]} - : op2[62:29]; - assign Float2[28:0] = op2[28:0] & {29{~conv_SP}}; - - // Set the sign of Float1 based on its original sign and if the operation - // is negation (op_type = 101) or absolute value (op_type = 100) - - assign Float1[63] = conv_SP ? op1[31] : op1[63]; - assign Float2[63] = conv_SP ? op2[31] : op2[63]; - -endmodule // convert_inputs - diff --git a/pipelined/src/fpu/convert_inputs_div.sv b/pipelined/src/fpu/convert_inputs_div.sv deleted file mode 100755 index 9d6d75c22..000000000 --- a/pipelined/src/fpu/convert_inputs_div.sv +++ /dev/null @@ -1,47 +0,0 @@ -// This module takes as inputs two operands (op1 and op2) -// and the result precision (P). Based on the operation and precision, -// it conditionally converts single precision values to double -// precision values and modifies the sign of op1. -// The converted operands are Float1 and Float2. -module convert_inputs_div ( - - input logic [63:0] op1, // 1st input operand (A) - input logic [63:0] op2, // 2nd input operand (B) - input logic P, // Result Precision (0 for double, 1 for single) - input logic op_type, // Operation - - output logic [63:0] Float1, // Converted 1st input operand - output logic [63:0] Float2b // Converted 2nd input operand -); - - logic [63:0] Float2; - logic Zexp1; // One if the exponent of op1 is zero - logic Zexp2; // One if the exponent of op2 is zero - logic Oexp1; // One if the exponent of op1 is all ones - logic Oexp2; // One if the exponent of op2 is all ones - - // Test if the input exponent is zero, because if it is then the - // exponent of the converted number should be zero. - assign Zexp1 = ~(|op1[30:23]); - assign Zexp2 = ~(|op2[30:23]); - assign Oexp1 = (&op1[30:23]); - assign Oexp2 = (&op2[30:23]); - - // Conditionally convert op1. Lower 29 bits are zero for single precision. - assign Float1[62:29] = P ? {op1[30], {3{(~op1[30]&~Zexp1)|Oexp1}}, op1[29:0]} - : op1[62:29]; - assign Float1[28:0] = op1[28:0] & {29{~P}}; - - // Conditionally convert op2. Lower 29 bits are zero for single precision. - assign Float2[62:29] = P ? {op2[30], {3{(~op2[30]&~Zexp2)|Oexp2}}, op2[29:0]} - : op2[62:29]; - assign Float2[28:0] = op2[28:0] & {29{~P}}; - - // Set the sign of Float1 based on its original sign - assign Float1[63] = P ? op1[31] : op1[63]; - assign Float2[63] = P ? op2[31] : op2[63]; - - // For sqrt, assign Float2 same as Float1 for simplicity - assign Float2b = op_type ? Float1 : Float2; - -endmodule // convert_inputs \ No newline at end of file diff --git a/pipelined/src/fpu/divconv.sv b/pipelined/src/fpu/divconv.sv deleted file mode 100755 index 8cc98cd01..000000000 --- a/pipelined/src/fpu/divconv.sv +++ /dev/null @@ -1,126 +0,0 @@ -/////////////////////////////////////////// -// -// Written: James Stine -// Modified: 9/28/2021 -// -// Purpose: Main convergence routine for floating point divider/square root unit (Goldschmidt) -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// MIT LICENSE -// Permission is hereby granted, free of charge, to any person obtaining a copy of this -// software and associated documentation files (the "Software"), to deal in the Software -// without restriction, including without limitation the rights to use, copy, modify, merge, -// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons -// to whom the Software is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or -// substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE -// OR OTHER DEALINGS IN THE SOFTWARE. -//////////////////////////////////////////////////////////////////////////////////////////////// - -module divconv ( - input logic [52:0] d, n, - input logic [2:0] sel_muxa, sel_muxb, - input logic sel_muxr, - input logic load_rega, load_regb, load_regc, load_regd, - input logic load_regr, load_regs, - input logic P, - input logic op_type, - input logic exp_odd, - input logic reset, - input logic clk, - - output logic [59:0] q1, qp1, qm1, - output logic [59:0] q0, qp0, qm0, - output logic [59:0] rega_out, regb_out, regc_out, regd_out, - output logic [119:0] regr_out -); - - logic [59:0] muxa_out, muxb_out; - logic [10:0] ia_div, ia_sqrt; - logic [59:0] ia_out; - logic [119:0] mul_out; - logic [59:0] q_out1, qm_out1, qp_out1; - logic [59:0] q_out0, qm_out0, qp_out0; - logic [59:0] mcand, mplier, mcand_q; - logic [59:0] twocmp_out; - logic [60:0] three; - logic [119:0] constant, constant2; - logic [59:0] q_const, qp_const, qm_const; - logic [59:0] d2, n2; - logic muxr_out; - logic cout1, cout2, cout3, cout4, cout5, cout6, cout7; - - // Check if exponent is odd for sqrt - // If exp_odd=1 and sqrt, then M/2 and use ia_addr=0 as IA - assign d2 = (exp_odd&op_type) ? {1'b0, d, 6'h0} : {d, 7'h0}; - assign n2 = op_type ? d2 : {n, 7'h0}; - - // IA div/sqrt - sbtm_div ia1 (d[52:41], ia_div); - sbtm_sqrt ia2 (d2[59:48], ia_sqrt); - assign ia_out = op_type ? {ia_sqrt, {49{1'b0}}} : {ia_div, {49{1'b0}}}; - - // Choose IA or iteration - mux6 #(60) mx1 (d2, ia_out, rega_out, regc_out, regd_out, regb_out, sel_muxb, muxb_out); - mux5 #(60) mx2 (regc_out, n2, ia_out, regb_out, regd_out, sel_muxa, muxa_out); - - // Deal with remainder if [0.5, 1) instead of [1, 2) - mux2 #(120) mx3a ({~n, {67{1'b1}}}, {{1'b1}, ~n, {66{1'b1}}}, q1[59], constant2); - // Select Mcand, Remainder/Q'' - mux2 #(120) mx3 (120'h0, constant2, sel_muxr, constant); - // Select mcand - remainder should always choose q1 [1,2) because - // adjustment of N in the from XX.FFFFFFF - mux2 #(60) mx4 (q0, q1, q1[59], mcand_q); - mux2 #(60) mx5 (muxb_out, mcand_q, sel_muxr&op_type, mplier); - mux2 #(60) mx6 (muxa_out, mcand_q, sel_muxr, mcand); - // Q*D - N (reversed but changed in rounder.v to account for sign reversal) - // Add ulp for subtraction in remainder - mux2 #(1) mx7 (1'b0, 1'b1, sel_muxr, muxr_out); - - // Constant for Q'' - mux2 #(60) mx8 ({60'h0000_0000_0000_020}, {60'h0000_0040_0000_000}, P, q_const); - mux2 #(60) mx9 ({60'h0000_0000_0000_0A0}, {60'h0000_0140_0000_000}, P, qp_const); - mux2 #(60) mxA ({60'hFFFF_FFFF_FFFF_F9F}, {60'hFFFF_FF3F_FFFF_FFF}, P, qm_const); - - // CPA (from CSA)/Remainder addition/subtraction - assign {cout1, mul_out} = (mcand*mplier) + constant + {119'b0, muxr_out}; - - // Assuming [1,2) - q1 - assign {cout2, q_out1} = regb_out + q_const; - assign {cout3, qp_out1} = regb_out + qp_const; - assign {cout4, qm_out1} = regb_out + qm_const + 1'b1; - // Assuming [0.5,1) - q0 - assign {cout5, q_out0} = {regb_out[58:0], 1'b0} + q_const; - assign {cout6, qp_out0} = {regb_out[58:0], 1'b0} + qp_const; - assign {cout7, qm_out0} = {regb_out[58:0], 1'b0} + qm_const + 1'b1; - - // One's complement instead of two's complement (for hw efficiency) - assign three = {~mul_out[118], mul_out[118], ~mul_out[117:59]}; - mux2 #(60) mxTC (~mul_out[118:59], three[60:1], op_type, twocmp_out); - - // regs - flopenr #(60) regc (clk, reset, load_regc, twocmp_out, regc_out); - flopenr #(60) regb (clk, reset, load_regb, mul_out[118:59], regb_out); - flopenr #(60) rega (clk, reset, load_rega, mul_out[118:59], rega_out); - flopenr #(60) regd (clk, reset, load_regd, mul_out[118:59], regd_out); - flopenr #(120) regr (clk, reset, load_regr, mul_out, regr_out); - // Assuming [1,2) - flopenr #(60) rege (clk, reset, load_regs, {q_out1[59:35], (q_out1[34:6] & {29{~P}}), 6'h0}, q1); - flopenr #(60) regf (clk, reset, load_regs, {qm_out1[59:35], (qm_out1[34:6] & {29{~P}}), 6'h0}, qm1); - flopenr #(60) regg (clk, reset, load_regs, {qp_out1[59:35], (qp_out1[34:6] & {29{~P}}), 6'h0}, qp1); - // Assuming [0,1) - flopenr #(60) regh (clk, reset, load_regs, {q_out0[59:35], (q_out0[34:6] & {29{~P}}), 6'h0}, q0); - flopenr #(60) regj (clk, reset, load_regs, {qm_out0[59:35], (qm_out0[34:6] & {29{~P}}), 6'h0}, qm0); - flopenr #(60) regk (clk, reset, load_regs, {qp_out0[59:35], (qp_out0[34:6] & {29{~P}}), 6'h0}, qp0); - -endmodule // divconv diff --git a/pipelined/src/fpu/divconv_pipe.sv b/pipelined/src/fpu/divconv_pipe.sv deleted file mode 100755 index 80dc8c7e8..000000000 --- a/pipelined/src/fpu/divconv_pipe.sv +++ /dev/null @@ -1,198 +0,0 @@ -/////////////////////////////////////////// -// -// Written: James Stine -// Modified: 8/1/2018 -// -// Purpose: Convergence unit for pipelined floating point divider/square root top unit (Goldschmidt) -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// MIT LICENSE -// Permission is hereby granted, free of charge, to any person obtaining a copy of this -// software and associated documentation files (the "Software"), to deal in the Software -// without restriction, including without limitation the rights to use, copy, modify, merge, -// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons -// to whom the Software is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or -// substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE -// OR OTHER DEALINGS IN THE SOFTWARE. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module divconv_pipe (q1, qm1, qp1, q0, qm0, qp0, rega_out, regb_out, regc_out, regd_out, - regr_out, d, n, sel_muxa, sel_muxb, sel_muxr, reset, clk, - load_rega, load_regb, load_regc, load_regd, load_regr, load_regs, load_regp, - P, op_type, exp_odd); - - input logic [52:0] d, n; - input logic [2:0] sel_muxa, sel_muxb; - input logic sel_muxr; - input logic load_rega, load_regb, load_regc, load_regd; - input logic load_regr, load_regs; - input logic load_regp; - input logic P; - input logic op_type; - input logic exp_odd; - input logic reset; - input logic clk; - - output logic [59:0] q1, qp1, qm1; - output logic [59:0] q0, qp0, qm0; - output logic [59:0] rega_out, regb_out, regc_out, regd_out; - output logic [119:0] regr_out; - - supply1 vdd; - supply0 vss; - - logic [59:0] muxa_out, muxb_out; - logic muxr_out; - logic [10:0] ia_div, ia_sqrt; - logic [59:0] ia_out; - logic [119:0] mul_out; - logic [59:0] q_out1, qm_out1, qp_out1; - logic [59:0] q_out0, qm_out0, qp_out0; - logic [59:0] mcand, mplier, mcand_q; - logic [59:0] twocmp_out; - logic [60:0] three; - logic [119:0] Carry, Carry2; - logic [119:0] Sum, Sum2; - logic [119:0] constant, constant2; - logic [59:0] q_const, qp_const, qm_const; - logic [59:0] d2, n2; - logic [11:0] d3; - - // Check if exponent is odd for sqrt - // If exp_odd=1 and sqrt, then M/2 and use ia_addr=0 as IA - assign d2 = (exp_odd&op_type) ? {vss, d, 6'h0} : {d, 7'h0}; - assign n2 = op_type ? d2 : {n, 7'h0}; - - // IA div/sqrt - sbtm_div ia1 (d[52:41], ia_div); - sbtm_sqrt ia2 (d2[59:48], ia_sqrt); - assign ia_out = op_type ? {ia_sqrt, {49{1'b0}}} : {ia_div, {49{1'b0}}}; - - // Choose IA or iteration - mux6 #(60) mx1 (d2, ia_out, rega_out, regc_out, regd_out, regb_out, sel_muxb, muxb_out); - mux5 #(60) mx2 (regc_out, n2, ia_out, regb_out, regd_out, sel_muxa, muxa_out); - - // Deal with remainder if [0.5, 1) instead of [1, 2) - mux2 #(120) mx3a ({~n, {67{1'b1}}}, {{1'b1}, ~n, {66{1'b1}}}, q1[59], constant2); - // Select Mcand, Remainder/Q'' - mux2 #(120) mx3 (120'h0, constant2, sel_muxr, constant); - // Select mcand - remainder should always choose q1 [1,2) because - // adjustment of N in the from XX.FFFFFFF - mux2 #(60) mx4 (q0, q1, q1[59], mcand_q); - mux2 #(60) mx5 (muxb_out, mcand_q, sel_muxr&op_type, mplier); - mux2 #(60) mx6 (muxa_out, mcand_q, sel_muxr, mcand); - // R4 Booth TDM multiplier (carry/save) - redundantmul #(60) bigmul(.a(mcand), .b(mplier), .out0(Sum), .out1(Carry)); - // Q*D - N (reversed but changed in rounder.v to account for sign reversal) - csa #(120) csa1 (Sum, Carry, constant, 1'b0, Sum2, Carry2); - // Add ulp for subtraction in remainder - mux2 #(1) mx7 (1'b0, 1'b1, sel_muxr, muxr_out); - - // Constant for Q'' - mux2 #(60) mx8 ({60'h0000_0000_0000_020}, {60'h0000_0040_0000_000}, P, q_const); - mux2 #(60) mx9 ({60'h0000_0000_0000_0A0}, {60'h0000_0140_0000_000}, P, qp_const); - mux2 #(60) mxA ({60'hFFFF_FFFF_FFFF_F9F}, {60'hFFFF_FF3F_FFFF_FFF}, P, qm_const); - - logic [119:0] Sum_pipe; - logic [119:0] Carry_pipe; - logic muxr_pipe; - logic rega_pipe; - logic regb_pipe; - logic regc_pipe; - logic regd_pipe; - logic regs_pipe; - logic regs_pipe2; - logic regr_pipe; - logic P_pipe; - logic op_type_pipe; - logic [59:0] q_const_pipe; - logic [59:0] qm_const_pipe; - logic [59:0] qp_const_pipe; - logic [59:0] q_const_pipe2; - logic [59:0] qm_const_pipe2; - logic [59:0] qp_const_pipe2; - - // Stage 1 - flopenr #(120) regp1 (clk, reset, load_regp, Sum2, Sum_pipe); - flopenr #(120) regp2 (clk, reset, load_regp, Carry2, Carry_pipe); - flopenr #(1) regp3 (clk, reset, load_regp, muxr_out, muxr_pipe); - - flopenr #(1) regp4 (clk, reset, load_regp, load_rega, rega_pipe); - flopenr #(1) regp5 (clk, reset, load_regp, load_regb, regb_pipe); - flopenr #(1) regp6 (clk, reset, load_regp, load_regc, regc_pipe); - flopenr #(1) regp7 (clk, reset, load_regp, load_regd, regd_pipe); - flopenr #(1) regp8 (clk, reset, load_regp, load_regs, regs_pipe); - flopenr #(1) regp9 (clk, reset, load_regp, load_regr, regr_pipe); - flopenr #(1) regpA (clk, reset, load_regp, P, P_pipe); - flopenr #(1) regpB (clk, reset, load_regp, op_type, op_type_pipe); - flopenr #(60) regpC (clk, reset, load_regp, q_const, q_const_pipe); - flopenr #(60) regpD (clk, reset, load_regp, qp_const, qp_const_pipe); - flopenr #(60) regpE (clk, reset, load_regp, qm_const, qm_const_pipe); - - // CPA (from CSA)/Remainder addition/subtraction - assign mul_out = Sum_pipe + Carry_pipe + {119'h0, muxr_pipe}; - // One's complement instead of two's complement (for hw efficiency) - assign three = {~mul_out[118] , mul_out[118], ~mul_out[117:59]}; - mux2 #(60) mxTC (~mul_out[118:59], three[60:1], op_type_pipe, twocmp_out); - - // Stage 2 - flopenr #(60) regc (clk, reset, regc_pipe, twocmp_out, regc_out); - flopenr #(60) regb (clk, reset, regb_pipe, mul_out[118:59], regb_out); - flopenr #(60) rega (clk, reset, rega_pipe, mul_out[118:59], rega_out); - flopenr #(60) regd (clk, reset, regd_pipe, mul_out[118:59], regd_out); - flopenr #(120) regr (clk, reset, regr_pipe, mul_out, regr_out); - flopenr #(1) regl (clk, reset, regs_pipe, regs_pipe, regs_pipe2); - flopenr #(60) regm (clk, reset, regs_pipe, q_const_pipe, q_const_pipe2); - flopenr #(60) regn (clk, reset, regs_pipe, qp_const_pipe, qp_const_pipe2); - flopenr #(60) rego (clk, reset, regs_pipe, qm_const_pipe, qm_const_pipe2); - - // Assuming [1,2) - q1 - assign q_out1 = regb_out + q_const; - assign qp_out1 = regb_out + qp_const; - assign qm_out1 = regb_out + qm_const + 1'b1; - // Assuming [0.5,1) - q0 - assign q_out0 = {regb_out[58:0], 1'b0} + q_const; - assign qp_out0 = {regb_out[58:0], 1'b0} + qp_const; - assign qm_out0 = {regb_out[58:0], 1'b0} + qm_const + 1'b1; - - // Stage 3 - // Assuming [1,2) - flopenr #(60) rege (clk, reset, regs_pipe2, {q_out1[59:35], (q_out1[34:6] & {29{~P_pipe}}), 6'h0}, q1); - flopenr #(60) regf (clk, reset, regs_pipe2, {qm_out1[59:35], (qm_out1[34:6] & {29{~P_pipe}}), 6'h0}, qm1); - flopenr #(60) regg (clk, reset, regs_pipe2, {qp_out1[59:35], (qp_out1[34:6] & {29{~P_pipe}}), 6'h0}, qp1); - // Assuming [0,1) - flopenr #(60) regh (clk, reset, regs_pipe2, {q_out0[59:35], (q_out0[34:6] & {29{~P_pipe}}), 6'h0}, q0); - flopenr #(60) regj (clk, reset, regs_pipe2, {qm_out0[59:35], (qm_out0[34:6] & {29{~P_pipe}}), 6'h0}, qm0); - flopenr #(60) regk (clk, reset, regs_pipe2, {qp_out0[59:35], (qp_out0[34:6] & {29{~P_pipe}}), 6'h0}, qp0); - -endmodule // divconv - -// *** rewrote behaviorally dh 5 Jan 2021 for speed -// module csa #(parameter WIDTH=8) ( -// input logic [WIDTH-1:0] a, b, c, -// output logic [WIDTH-1:0] sum, carry); - -// assign sum = a ^ b ^ c; -// assign carry = (a & (b | c)) | (b & c); -// /* -// logic [WIDTH:0] carry_temp; -// genvar i; -// for (i=0;i" prompt: -# do wally-pipelined.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do wally-pipelined.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -vlog +incdir+../config/rv64gc +incdir+../config/shared srt-radix4.sv testbench-radix4.sv ../src/generic/flop/flop*.sv ../src/generic/mux.sv ../src/generic/lzc.sv -vopt +acc work.testbenchradix4 -o workopt -vsim workopt - --- display input and output signals as hexidecimal values -add wave /testbenchradix4/* -add wave /testbenchradix4/srtradix4/* -add wave /testbenchradix4/srtradix4/qsel4/* -add wave /testbenchradix4/srtradix4/otfc4/* - --- Run the Simulation -run -all diff --git a/pipelined/srt/testbench-radix4.sv b/pipelined/srt/testbench-radix4.sv deleted file mode 100644 index 434ef74b0..000000000 --- a/pipelined/srt/testbench-radix4.sv +++ /dev/null @@ -1,122 +0,0 @@ - -`include "wally-config.vh" -`define DIVLEN ((`NF<`XLEN) ? `XLEN : `NF) - -/////////// -// clock // -/////////// -module clock(clk); - output clk; - - // Internal clk signal - logic clk; - -endmodule - -////////// -// testbench // -////////// -module testbenchradix4; - logic clk; - logic req; - logic DivDone; - logic [63:0] a, b; - logic [51:0] afrac, bfrac; - logic [10:0] aExp, bExp; - logic asign, bsign; - logic [51:0] r, rOTFC; - logic [`DIVLEN-1:0] Quot, QuotOTFC; - logic [54:0] rp, rm; // positive quotient digits - - // Test parameters - parameter MEM_SIZE = 40000; - parameter MEM_WIDTH = 64+64+64; - - `define memr 63:0 - `define memb 127:64 - `define mema 191:128 - - // Test logicisters - logic [MEM_WIDTH-1:0] Tests [0:MEM_SIZE]; // Space for input file - logic [MEM_WIDTH-1:0] Vec; // Verilog doesn't allow direct access to a - // bit field of an array - logic [63:0] correctr, nextr, diffn, diffp; - logic [10:0] DivExp; - logic DivSgn; - integer testnum, errors; - - // Divider - srtradix4 srtradix4(.clk, .DivStart(req), - .XExpE(aExp), .YExpE(bExp), .DivExp, - .XSgnE(asign), .YSgnE(bsign), .DivSgn, - .XFrac(afrac), .YFrac(bfrac), - .SrcA('0), .SrcB('0), - .W64(1'b0), .Signed(1'b0), .Int(1'b0), .Sqrt(1'b0), .DivDone, - .Quot, .Rem()); - - // Counter - - - initial - forever - begin - clk = 1; #17; - clk = 0; #17; - end - - - // Read test vectors from disk - initial - begin - testnum = 0; - errors = 0; - $readmemh ("testvectors", Tests); - Vec = Tests[testnum]; - a = Vec[`mema]; - {asign, aExp, afrac} = a; - b = Vec[`memb]; - {bsign, bExp, bfrac} = b; - nextr = Vec[`memr]; - r = Quot[`DIVLEN-1:`DIVLEN - 52]; - req <= 1; - end - - // Apply directed test vectors read from file. - - always @(posedge clk) - begin - r = Quot[`DIVLEN-1:`DIVLEN - 52]; - if (DivDone) begin - req <= 1; - diffp = correctr[51:0] - r; - diffn = r - correctr[51:0]; - if ((DivSgn !== correctr[63]) | (DivExp !== correctr[62:52]) | ($signed(diffn) > 1) | ($signed(diffp) > 1) | (diffn === 64'bx) | (diffp === 64'bx)) // check if accurate to 1 ulp - begin - errors = errors+1; - $display("result was %h_%h, should be %h %h %h\n", DivExp, r, correctr, diffn, diffp); - $display("failed\n"); - $stop; - end - if (afrac === 52'hxxxxxxxxxxxxx) - begin - $display("%d Tests completed successfully", testnum); - $stop; - end - end - if (req) - begin - req <= 0; - correctr = nextr; - testnum = testnum+1; - Vec = Tests[testnum]; - $display("a = %h b = %h",a,b); - a = Vec[`mema]; - {asign, aExp, afrac} = a; - b = Vec[`memb]; - {bsign, bExp, bfrac} = b; - nextr = Vec[`memr]; - end - end - -endmodule -