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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Refactored SPI peripheral based on SPI controller module. Works in tests/custom/spitest.
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@ -62,10 +62,6 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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localparam SPI_IE = 8'h70;
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localparam SPI_IE = 8'h70;
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localparam SPI_IP = 8'h74;
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localparam SPI_IP = 8'h74;
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// receive shift register states
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typedef enum logic [1:0] {ReceiveShiftFullState, ReceiveShiftNotFullState, ReceiveShiftDelayState} rsrstatetype;
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// SPI control registers. Refer to SiFive FU540-C000 manual
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// SPI control registers. Refer to SiFive FU540-C000 manual
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logic [11:0] SckDiv;
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logic [11:0] SckDiv;
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logic [1:0] SckMode;
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logic [1:0] SckMode;
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@ -75,89 +71,68 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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logic [15:0] Delay0, Delay1;
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logic [15:0] Delay0, Delay1;
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logic [4:0] Format;
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logic [4:0] Format;
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logic [7:0] ReceiveData;
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logic [7:0] ReceiveData;
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logic [2:0] TransmitWatermark, ReceiveWatermark;
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logic [8:0] TransmitData;
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logic [8:0] TransmitData;
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logic [2:0] TransmitWatermark, ReceiveWatermark;
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logic [1:0] InterruptEnable, InterruptPending;
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logic [1:0] InterruptEnable, InterruptPending;
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// Bus interface signals
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// Bus interface signals
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logic [7:0] Entry;
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logic [7:0] Entry;
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logic Memwrite;
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logic Memwrite;
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logic [31:0] Din, Dout;
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logic [31:0] Din, Dout;
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logic TransmitInactive; // High when there is no transmission, used as hardware interlock signal
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// SPI Controller signals
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logic SCLKenable;
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logic EndOfFrame;
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logic EndOfFrameDelay;
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logic Transmitting;
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logic InactiveState;
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logic ResetSCLKenable;
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logic TransmitStart;
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// Transmit Start State Machine Variables
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typedef enum logic [1:0] {READY, START, WAIT} txState;
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txState CurrState, NextState;
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// FIFO FSM signals
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// FIFO FSM signals
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// Watermark signals - TransmitReadMark = ip[0], ReceiveWriteMark = ip[1]
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// Watermark signals - TransmitReadMark = ip[0], ReceiveWriteMark = ip[1]
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logic TransmitWriteMark, TransmitReadMark, RecieveWriteMark, RecieveReadMark;
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logic TransmitWriteMark, TransmitReadMark, RecieveWriteMark, RecieveReadMark;
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logic TransmitFIFOWriteFull, TransmitFIFOReadEmpty;
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logic TransmitFIFOWriteFull, TransmitFIFOReadEmpty;
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logic TransmitFIFOWriteIncrement;
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logic TransmitFIFOWriteIncrement;
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logic ReceiveFiFoWriteInc;
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logic [7:0] TransmitFIFOReadData;
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logic ReceiveFIFOWriteInc;
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logic ReceiveFIFOReadIncrement;
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logic ReceiveFIFOReadIncrement;
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logic ReceiveFIFOWriteFull, ReceiveFIFOReadEmpty;
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logic ReceiveFIFOWriteFull, ReceiveFIFOReadEmpty;
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logic [7:0] TransmitFIFOReadData;
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/* verilator lint_off UNDRIVEN */
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/* verilator lint_off UNDRIVEN */
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logic [2:0] TransmitWriteWatermarkLevel, ReceiveReadWatermarkLevel; // unused generic FIFO outputs
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logic [2:0] TransmitWriteWatermarkLevel, ReceiveReadWatermarkLevel; // unused generic FIFO outputs
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/* verilator lint_off UNDRIVEN */
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/* verilator lint_off UNDRIVEN */
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logic [7:0] ReceiveShiftRegEndian; // Reverses ReceiveShiftReg if Format[2] set (little endian transmission)
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logic [7:0] ReceiveShiftRegEndian; // Reverses ReceiveShiftReg if Format[2] set (little endian transmission)
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rsrstatetype ReceiveState;
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logic ReceiveFiFoTakingData;
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// Transmission signals
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logic ZeroDiv; // High when SckDiv is 0
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logic [11:0] DivCounter; // Counter for sck
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logic SCLKenable; // Flip flop enable high every sclk edge
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// Delay signals
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logic [8:0] ImplicitDelay1; // Adds implicit delay to cs-sck delay counter based on phase
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logic [8:0] ImplicitDelay2; // Adds implicit delay to sck-cs delay counter based on phase
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logic [8:0] CS_SCKCount; // Counter for cs-sck delay
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logic [8:0] SCK_CSCount; // Counter for sck-cs delay
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logic [8:0] InterCSCount; // Counter for inter cs delay
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logic [8:0] InterXFRCount; // Counter for inter xfr delay
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logic ZeroDelayHoldMode; // High when ChipSelectMode is hold and Delay1[15:8] (InterXFR delay) is 0
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// Frame counting signals
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logic FirstFrame;
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logic [3:0] FrameCount; // Counter for number of frames in transmission
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logic ReceivePenultimateFrame; // High when penultimate frame in transmission has been reached
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// State fsm signals
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logic Active; // High when state is either Active1 or Active0 (during transmission)
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logic Active0; // High when state is Active0
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// Shift reg signals
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// Shift reg signals
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logic ShiftEdge; // Determines which edge of sck to shift from TransmitShiftReg
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logic ShiftEdge; // Determines which edge of sck to shift from TransmitReg
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logic [7:0] TransmitShiftReg; // Transmit shift register
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logic [7:0] ReceiveShiftReg; // Receive shift register
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logic SampleEdge; // Determines which edge of sck to sample from ReceiveShiftReg
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logic SampleEdge; // Determines which edge of sck to sample from ReceiveShiftReg
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logic [7:0] TransmitReg; // Transmit shift register
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logic [7:0] ReceiveShiftReg; // Receive shift register
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logic [7:0] TransmitDataEndian; // Reverses TransmitData from txFIFO if littleendian, since TransmitReg always shifts MSB
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logic [7:0] TransmitDataEndian; // Reverses TransmitData from txFIFO if littleendian, since TransmitReg always shifts MSB
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logic TransmitShiftRegLoad; // Determines when to load TransmitShiftReg
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logic TransmitLoad; // Determines when to load TransmitReg
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logic TransmitShiftRegLoadSingleCycle; // Version of TransmitShiftRegLoad which is only high for a single SCLK cycle to prevent double loads
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logic TransmitShiftRegLoadDelay; // TransmitShiftRegLoad delayed by an SCLK cycle, inverted and anded with TransmitShiftRegLoad to create a single cycle signal
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logic TransmitFIFOReadIncrement; // Increments Tx FIFO read ptr 1 cycle after Tx FIFO is read
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logic TransmitFIFOReadIncrement; // Increments Tx FIFO read ptr 1 cycle after Tx FIFO is read
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logic ReceiveShiftFull; // High when receive shift register is full
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logic TransmitShiftEmpty; // High when transmit shift register is empty
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// Shift stuff due to Format register?
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logic ShiftIn; // Determines whether to shift from SPIIn or SPIOut (if SPI_LOOPBACK_TEST)
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logic ShiftIn; // Determines whether to shift from SPIIn or SPIOut (if SPI_LOOPBACK_TEST)
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logic [3:0] LeftShiftAmount; // Determines left shift amount to left-align data when little endian
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logic [3:0] LeftShiftAmount; // Determines left shift amount to left-align data when little endian
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logic [7:0] ASR; // AlignedReceiveShiftReg
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logic [7:0] ASR; // AlignedReceiveShiftReg
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logic ShiftEdgeSPICLK; // Changes ShiftEdge when SckDiv is 0
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// CS signals
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// CS signals
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logic [3:0] ChipSelectAuto; // Assigns ChipSelect value to selected CS signal based on CS ID
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logic [3:0] ChipSelectAuto; // Assigns ChipSelect value to selected CS signal based on CS ID
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logic [3:0] ChipSelectInternal; // Defines what each ChipSelect signal should be based on transmission status and ChipSelectDef
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logic [3:0] ChipSelectInternal; // Defines what each ChipSelect signal should be based on transmission status and ChipSelectDef
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logic DelayMode; // Determines where to place implicit half cycle delay based on sck phase for CS assertion
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// Miscellaneous signals delayed/early by 1 PCLK cycle
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logic ReceiveShiftFullDelay; // Delays ReceiveShiftFull signal by 1 PCLK cycle
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logic ReceiveShiftFullDelayPCLK; // ReceiveShiftFull delayed by 1 PCLK cycle
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logic TransmitFIFOReadEmptyDelay;
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logic SCLKenableEarly; // SCLKenable 1 PCLK cycle early, needed for on time register changes when ChipSelectMode is hold and Delay1[15:8] (InterXFR delay) is 0
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// APB access
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// APB access
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assign Entry = {PADDR[7:2],2'b00}; // 32-bit word-aligned accesses
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assign Entry = {PADDR[7:2],2'b00}; // 32-bit word-aligned accesses
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assign Memwrite = PWRITE & PENABLE & PSEL; // Only write in access phase
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assign Memwrite = PWRITE & PENABLE & PSEL; // Only write in access phase
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assign PREADY = Entry == SPI_TXDATA | Entry == SPI_RXDATA | Entry == SPI_IP | TransmitInactive; // Tie PREADY to transmission for hardware interlock
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// assign PREADY = Entry == SPI_TXDATA | Entry == SPI_RXDATA | Entry == SPI_IP;
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assign PREADY = 1'b1;
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// Account for subword read/write circuitry
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// Account for subword read/write circuitry
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// -- Note SPI registers are 32 bits no matter what; access them with LW SW.
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// -- Note SPI registers are 32 bits no matter what; access them with LW SW.
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@ -183,10 +158,8 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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InterruptEnable <= 2'b0;
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InterruptEnable <= 2'b0;
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InterruptPending <= 2'b0;
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InterruptPending <= 2'b0;
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end else begin // writes
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end else begin // writes
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/* verilator lint_off CASEINCOMPLETE */
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/* verilator lint_off CASEINCOMPLETE */
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if (Memwrite & TransmitInactive)
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if (Memwrite)
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case(Entry) // flop to sample inputs
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case(Entry) // flop to sample inputs
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SPI_SCKDIV: SckDiv <= Din[11:0];
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SPI_SCKDIV: SckDiv <= Din[11:0];
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SPI_SCKMODE: SckMode <= Din[1:0];
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SPI_SCKMODE: SckMode <= Din[1:0];
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@ -234,227 +207,121 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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// SPI enable generation, where SCLK = PCLK/(2*(SckDiv + 1))
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// SPI enable generation, where SCLK = PCLK/(2*(SckDiv + 1))
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// Asserts SCLKenable at the rising and falling edge of SCLK by counting from 0 to SckDiv
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// Asserts SCLKenable at the rising and falling edge of SCLK by counting from 0 to SckDiv
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// Active at 2x SCLK frequency to account for implicit half cycle delays and actions on both clock edges depending on phase
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// Active at 2x SCLK frequency to account for implicit half cycle delays and actions on both clock edges depending on phase
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// When SckDiv is 0, count doesn't work and SCLKenable is simply PCLK *** dh 10/26/24: this logic is seriously broken. SCLK is not scaled to PCLK/(2*(SckDiv + 1)). SCLKenableEarly doesn't work right for SckDiv=0
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// When SckDiv is 0, count doesn't work and SCLKenable is simply PCLK *** dh 10/26/24: this logic is seriously broken. SCLK is not scaled to PCLK/(2*(SckDiv + 1)).
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assign ZeroDiv = ~|(SckDiv[10:0]);
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assign SCLKenable = ZeroDiv ? 1 : (DivCounter == SckDiv);
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assign SCLKenableEarly = ((DivCounter + 12'b1) == SckDiv);
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always_ff @(posedge PCLK)
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if (~PRESETn) DivCounter <= '0;
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else if (SCLKenable) DivCounter <= 12'b0;
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else DivCounter <= DivCounter + 12'b1;
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// Asserts when transmission is one frame before complete
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// SPI Controller module -------------------------------------------
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assign ReceivePenultimateFrame = ((FrameCount + 4'b0001) == Format[4:1]);
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// This module controls state and timing signals that drive the rest of this module
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assign FirstFrame = (FrameCount == 4'b0);
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assign ResetSCLKenable = Memwrite & (Entry == SPI_SCKDIV);
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// Computing delays
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spi_controller controller(PCLK, PRESETn,
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// When sckmode.pha = 0, an extra half-period delay is implicit in the cs-sck delay, and vice-versa for sck-cs
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// Transmit Signals
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assign ImplicitDelay1 = SckMode[0] ? 9'b0 : 9'b1;
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TransmitStart, ResetSCLKenable,
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assign ImplicitDelay2 = SckMode[0] ? 9'b1 : 9'b0;
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// Register Inputs
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SckDiv, SckMode, ChipSelectMode, Delay0, Delay1,
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// Calculate when tx/rx shift registers are full/empty
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// txFIFO stuff
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TransmitFIFOReadEmpty,
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// Transmit Shift FSM
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// Timing
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always_ff @(posedge PCLK)
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SCLKenable, ShiftEdge, SampleEdge, EndOfFrame, EndOfFrameDelay,
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if (~PRESETn) TransmitShiftEmpty <= 1'b1;
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// State stuff
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else if (TransmitShiftEmpty) begin
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Transmitting, InactiveState,
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if (TransmitFIFOReadEmpty | (~TransmitFIFOReadEmpty & (ReceivePenultimateFrame & Active0))) TransmitShiftEmpty <= 1'b1;
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// Outputs
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else if (~TransmitFIFOReadEmpty) TransmitShiftEmpty <= 1'b0;
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SPICLK);
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end else begin
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if (ReceivePenultimateFrame & Active0) TransmitShiftEmpty <= 1'b1;
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else TransmitShiftEmpty <= 1'b0;
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end
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// Receive Shift FSM
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always_ff @(posedge PCLK)
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if (~PRESETn) ReceiveState <= ReceiveShiftNotFullState;
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else if (SCLKenable) begin
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case (ReceiveState)
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ReceiveShiftFullState: ReceiveState <= ReceiveShiftNotFullState;
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ReceiveShiftNotFullState: if (ReceivePenultimateFrame & (SampleEdge)) ReceiveState <= ReceiveShiftDelayState;
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else ReceiveState <= ReceiveShiftNotFullState;
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ReceiveShiftDelayState: ReceiveState <= ReceiveShiftFullState;
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endcase
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end
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assign ReceiveShiftFull = SckMode[0] ? (ReceiveState == ReceiveShiftFullState) : (ReceiveState == ReceiveShiftDelayState);
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// Calculate tx/rx fifo write and recieve increment signals
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always_ff @(posedge PCLK)
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if (~PRESETn) TransmitFIFOWriteIncrement <= 1'b0;
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else TransmitFIFOWriteIncrement <= (Memwrite & (Entry == SPI_TXDATA) & ~TransmitFIFOWriteFull);
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always_ff @(posedge PCLK)
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if (~PRESETn) ReceiveFIFOReadIncrement <= 1'b0;
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else ReceiveFIFOReadIncrement <= ((Entry == SPI_RXDATA) & ~ReceiveFIFOReadEmpty & PSEL & ~ReceiveFIFOReadIncrement);
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assign TransmitShiftRegLoad = ~TransmitShiftEmpty & ~Active | (((ChipSelectMode == 2'b10) & ~|(Delay1[15:8])) & ((ReceiveShiftFullDelay | ReceiveShiftFull) & ~SampleEdge & ~TransmitFIFOReadEmpty));
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always_ff @(posedge PCLK)
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if (~PRESETn) TransmitShiftRegLoadDelay <=0;
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else if (SCLKenable) TransmitShiftRegLoadDelay <= TransmitShiftRegLoad;
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assign TransmitShiftRegLoadSingleCycle = TransmitShiftRegLoad & ~TransmitShiftRegLoadDelay;
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always_ff @(posedge PCLK)
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if (~PRESETn) TransmitFIFOReadIncrement <= 0;
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else if (SCLKenable) TransmitFIFOReadIncrement <= TransmitShiftRegLoadSingleCycle;
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// Tx/Rx FIFOs
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spi_fifo #(3,8) txFIFO(PCLK, 1'b1, SCLKenable, PRESETn, TransmitFIFOWriteIncrement, TransmitFIFOReadIncrement, TransmitData[7:0], TransmitWriteWatermarkLevel, TransmitWatermark[2:0],
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TransmitFIFOReadData[7:0], TransmitFIFOWriteFull, TransmitFIFOReadEmpty, TransmitWriteMark, TransmitReadMark);
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spi_fifo #(3,8) rxFIFO(PCLK, SCLKenable, 1'b1, PRESETn, ReceiveFiFoWriteInc, ReceiveFIFOReadIncrement, ReceiveShiftRegEndian, ReceiveWatermark[2:0], ReceiveReadWatermarkLevel,
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ReceiveData[7:0], ReceiveFIFOWriteFull, ReceiveFIFOReadEmpty, RecieveWriteMark, RecieveReadMark);
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always_ff @(posedge PCLK)
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if (~PRESETn) TransmitFIFOReadEmptyDelay <= 1'b1;
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else if (SCLKenable) TransmitFIFOReadEmptyDelay <= TransmitFIFOReadEmpty;
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always_ff @(posedge PCLK)
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if (~PRESETn) ReceiveShiftFullDelay <= 1'b0;
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else if (SCLKenable) ReceiveShiftFullDelay <= ReceiveShiftFull;
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assign ReceiveFiFoTakingData = ReceiveFiFoWriteInc & ~ReceiveFIFOWriteFull;
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always_ff @(posedge PCLK)
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if (~PRESETn) ReceiveFiFoWriteInc <= 1'b0;
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else if (SCLKenable & ReceiveShiftFull) ReceiveFiFoWriteInc <= 1'b1;
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else if (SCLKenable & ReceiveFiFoTakingData) ReceiveFiFoWriteInc <= 1'b0;
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always_ff @(posedge PCLK)
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if (~PRESETn) ReceiveShiftFullDelayPCLK <= 1'b0;
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else if (SCLKenableEarly) ReceiveShiftFullDelayPCLK <= ReceiveShiftFull;
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// Main FSM which controls SPI transmission
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typedef enum logic [2:0] {CS_INACTIVE, DELAY_0, ACTIVE_0, ACTIVE_1, DELAY_1,INTER_CS, INTER_XFR} statetype;
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statetype state;
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// Transmit FIFO ---------------------------------------------------
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always_ff @(posedge PCLK)
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always_ff @(posedge PCLK)
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if (~PRESETn) begin
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if (~PRESETn) begin
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state <= CS_INACTIVE;
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TransmitFIFOWriteIncrement <= 1'b0;
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FrameCount <= 4'b0;
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TransmitFIFOReadIncrement <= 1'b0;
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SPICLK <= SckMode[1];
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end else begin
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TransmitFIFOWriteIncrement <= (Memwrite & (Entry == SPI_TXDATA) & ~TransmitFIFOWriteFull);
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TransmitFIFOReadIncrement <= TransmitLoad;
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end
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// Setup TransmitStart state machine
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always_ff @(posedge PCLK) begin
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if (~PRESETn) begin
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CurrState <= READY;
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end else if (SCLKenable) begin
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end else if (SCLKenable) begin
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/* verilator lint_off CASEINCOMPLETE */
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CurrState <= NextState;
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case (state)
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CS_INACTIVE: begin
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CS_SCKCount <= 9'b1;
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SCK_CSCount <= 9'b10;
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FrameCount <= 4'b0;
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InterCSCount <= 9'b10;
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InterXFRCount <= 9'b1;
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if ((~TransmitFIFOReadEmpty | ~TransmitShiftEmpty) & ((|(Delay0[7:0])) | ~SckMode[0])) state <= DELAY_0;
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else if ((~TransmitFIFOReadEmpty | ~TransmitShiftEmpty)) begin
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state <= ACTIVE_0;
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SPICLK <= ~SckMode[1];
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end else SPICLK <= SckMode[1];
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end
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DELAY_0: begin
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|
||||||
CS_SCKCount <= CS_SCKCount + 9'b1;
|
|
||||||
if (CS_SCKCount >= (({Delay0[7:0], 1'b0}) + ImplicitDelay1)) begin
|
|
||||||
state <= ACTIVE_0;
|
|
||||||
SPICLK <= ~SckMode[1];
|
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
ACTIVE_0: begin
|
|
||||||
FrameCount <= FrameCount + 4'b1;
|
// State machine for starting transmissions
|
||||||
SPICLK <= SckMode[1];
|
always_comb begin
|
||||||
state <= ACTIVE_1;
|
case (CurrState)
|
||||||
end
|
READY: if (~TransmitFIFOReadEmpty) NextState = START;
|
||||||
ACTIVE_1: begin
|
else NextState = READY;
|
||||||
InterXFRCount <= 9'b1;
|
START: NextState = WAIT;
|
||||||
if (FrameCount < Format[4:1]) begin
|
WAIT: if (TransmitFIFOReadEmpty & ~Transmitting) NextState = READY;
|
||||||
state <= ACTIVE_0;
|
else NextState = WAIT;
|
||||||
SPICLK <= ~SckMode[1];
|
|
||||||
end
|
|
||||||
else if ((ChipSelectMode[1:0] == 2'b10) & ~|(Delay1[15:8]) & (~TransmitFIFOReadEmpty)) begin
|
|
||||||
state <= ACTIVE_0;
|
|
||||||
SPICLK <= ~SckMode[1];
|
|
||||||
CS_SCKCount <= 9'b1;
|
|
||||||
SCK_CSCount <= 9'b10;
|
|
||||||
FrameCount <= 4'b0;
|
|
||||||
InterCSCount <= 9'b10;
|
|
||||||
end
|
|
||||||
else if (ChipSelectMode[1:0] == 2'b10) state <= INTER_XFR;
|
|
||||||
else if (~|(Delay0[15:8]) & (~SckMode[0])) state <= INTER_CS;
|
|
||||||
else state <= DELAY_1;
|
|
||||||
end
|
|
||||||
DELAY_1: begin
|
|
||||||
SCK_CSCount <= SCK_CSCount + 9'b1;
|
|
||||||
if (SCK_CSCount >= (({Delay0[15:8], 1'b0}) + ImplicitDelay2)) state <= INTER_CS;
|
|
||||||
end
|
|
||||||
INTER_CS: begin
|
|
||||||
InterCSCount <= InterCSCount + 9'b1;
|
|
||||||
SPICLK <= SckMode[1];
|
|
||||||
if (InterCSCount >= ({Delay1[7:0],1'b0})) state <= CS_INACTIVE;
|
|
||||||
end
|
|
||||||
INTER_XFR: begin
|
|
||||||
CS_SCKCount <= 9'b1;
|
|
||||||
SCK_CSCount <= 9'b10;
|
|
||||||
FrameCount <= 4'b0;
|
|
||||||
InterCSCount <= 9'b10;
|
|
||||||
InterXFRCount <= InterXFRCount + 9'b1;
|
|
||||||
if ((InterXFRCount >= ({Delay1[15:8], 1'b0})) & (~TransmitFIFOReadEmptyDelay | ~TransmitShiftEmpty)) begin
|
|
||||||
state <= ACTIVE_0;
|
|
||||||
SPICLK <= ~SckMode[1];
|
|
||||||
end else if (~|ChipSelectMode[1:0]) state <= CS_INACTIVE;
|
|
||||||
else SPICLK <= SckMode[1];
|
|
||||||
end
|
|
||||||
endcase
|
endcase
|
||||||
/* verilator lint_off CASEINCOMPLETE */
|
|
||||||
end
|
end
|
||||||
|
|
||||||
|
assign TransmitStart = (CurrState == START);
|
||||||
|
|
||||||
|
spi_fifo #(3,8) txFIFO(PCLK, 1'b1, SCLKenable, PRESETn,
|
||||||
|
TransmitFIFOWriteIncrement, TransmitFIFOReadIncrement,
|
||||||
|
TransmitData[7:0],
|
||||||
|
TransmitWriteWatermarkLevel, TransmitWatermark[2:0],
|
||||||
|
TransmitFIFOReadData[7:0],
|
||||||
|
TransmitFIFOWriteFull,
|
||||||
|
TransmitFIFOReadEmpty,
|
||||||
|
TransmitWriteMark, TransmitReadMark);
|
||||||
|
|
||||||
|
|
||||||
assign DelayMode = SckMode[0] ? (state == DELAY_1) : (state == ACTIVE_1 & ReceiveShiftFull);
|
// Receive FIFO ----------------------------------------------------
|
||||||
assign ChipSelectInternal = (state == CS_INACTIVE | state == INTER_CS | DelayMode & ~|(Delay0[15:8])) ? ChipSelectDef : ~ChipSelectDef;
|
always_ff @(posedge PCLK)
|
||||||
assign Active = (state == ACTIVE_0 | state == ACTIVE_1);
|
if (~PRESETn) begin
|
||||||
assign SampleEdge = SckMode[0] ? (state == ACTIVE_1) : (state == ACTIVE_0);
|
ReceiveFIFOReadIncrement <= 1'b0;
|
||||||
assign ZeroDelayHoldMode = ((ChipSelectMode == 2'b10) & (~|(Delay1[7:4])));
|
ReceiveFIFOWriteInc <= 1'b0;
|
||||||
assign TransmitInactive = ((state == INTER_CS) | (state == CS_INACTIVE) | (state == INTER_XFR) | (ReceiveShiftFullDelayPCLK & ZeroDelayHoldMode) | ((state == ACTIVE_1) & ((ChipSelectMode[1:0] == 2'b10) & ~|(Delay1[15:8]) & (~TransmitFIFOReadEmpty) & (FrameCount == Format[4:1]))));
|
end else begin
|
||||||
assign Active0 = (state == ACTIVE_0);
|
ReceiveFIFOReadIncrement <= ((Entry == SPI_RXDATA) & ~ReceiveFIFOReadEmpty & PSEL & ~ReceiveFIFOReadIncrement);
|
||||||
assign ShiftEdgeSPICLK = ZeroDiv ? ~SPICLK : SPICLK;
|
ReceiveFIFOWriteInc <= EndOfFrameDelay;
|
||||||
|
end
|
||||||
|
|
||||||
// Signal tracks which edge of sck to shift data
|
spi_fifo #(3,8) rxFIFO(PCLK, SCLKenable, 1'b1, PRESETn,
|
||||||
always_comb
|
ReceiveFIFOWriteInc, ReceiveFIFOReadIncrement,
|
||||||
case(SckMode[1:0])
|
ReceiveShiftRegEndian, ReceiveWatermark[2:0],
|
||||||
2'b00: ShiftEdge = ShiftEdgeSPICLK & SCLKenable;
|
ReceiveReadWatermarkLevel,
|
||||||
2'b01: ShiftEdge = (~ShiftEdgeSPICLK & ~FirstFrame & (|(FrameCount) | (CS_SCKCount >= (({Delay0[7:0], 1'b0}) + ImplicitDelay1))) & SCLKenable & (FrameCount != Format[4:1]) & ~TransmitInactive);
|
ReceiveData[7:0],
|
||||||
2'b10: ShiftEdge = ~ShiftEdgeSPICLK & SCLKenable;
|
ReceiveFIFOWriteFull,
|
||||||
2'b11: ShiftEdge = (ShiftEdgeSPICLK & ~FirstFrame & (|(FrameCount) | (CS_SCKCount >= (({Delay0[7:0], 1'b0}) + ImplicitDelay1))) & SCLKenable & (FrameCount != Format[4:1]) & ~TransmitInactive);
|
ReceiveFIFOReadEmpty,
|
||||||
default: ShiftEdge = ShiftEdgeSPICLK & SCLKenable;
|
RecieveWriteMark, RecieveReadMark);
|
||||||
endcase
|
|
||||||
|
|
||||||
// Transmit shift register
|
// Transmit shift register
|
||||||
assign TransmitDataEndian = Format[0] ? {TransmitFIFOReadData[0], TransmitFIFOReadData[1], TransmitFIFOReadData[2], TransmitFIFOReadData[3], TransmitFIFOReadData[4], TransmitFIFOReadData[5], TransmitFIFOReadData[6], TransmitFIFOReadData[7]} : TransmitFIFOReadData[7:0];
|
assign TransmitLoad = TransmitStart | (EndOfFrameDelay & ~TransmitFIFOReadEmpty);
|
||||||
|
assign TransmitDataEndian = Format[0] ? {<<{TransmitFIFOReadData[7:0]}} : TransmitFIFOReadData[7:0];
|
||||||
always_ff @(posedge PCLK)
|
always_ff @(posedge PCLK)
|
||||||
if(~PRESETn) TransmitShiftReg <= 8'b0;
|
if(~PRESETn) TransmitReg <= 8'b0;
|
||||||
else if (TransmitShiftRegLoadSingleCycle) TransmitShiftReg <= TransmitDataEndian;
|
else if (TransmitLoad) TransmitReg <= TransmitDataEndian;
|
||||||
else if (ShiftEdge & Active) TransmitShiftReg <= {TransmitShiftReg[6:0], TransmitShiftReg[0]};
|
else if (ShiftEdge) TransmitReg <= {TransmitReg[6:0], TransmitReg[0]};
|
||||||
|
|
||||||
assign SPIOut = TransmitShiftReg[7];
|
assign SPIOut = TransmitReg[7];
|
||||||
|
|
||||||
// If in loopback mode, receive shift register is connected directly to module's output pins. Else, connected to SPIIn
|
// If in loopback mode, receive shift register is connected directly
|
||||||
// There are no setup/hold time issues because transmit shift register and receive shift register always shift/sample on opposite edges
|
// to module's output pins. Else, connected to SPIIn. There are no
|
||||||
|
// setup/hold time issues because transmit shift register and receive
|
||||||
|
// shift register always shift/sample on opposite edges
|
||||||
assign ShiftIn = P.SPI_LOOPBACK_TEST ? SPIOut : SPIIn;
|
assign ShiftIn = P.SPI_LOOPBACK_TEST ? SPIOut : SPIIn;
|
||||||
|
|
||||||
// Receive shift register
|
// Receive shift register
|
||||||
always_ff @(posedge PCLK)
|
always_ff @(posedge PCLK)
|
||||||
if(~PRESETn) ReceiveShiftReg <= 8'b0;
|
if(~PRESETn) ReceiveShiftReg <= 8'b0;
|
||||||
else if (SampleEdge & SCLKenable) begin
|
else if (SampleEdge) begin
|
||||||
if (~Active) ReceiveShiftReg <= 8'b0;
|
if (~Transmitting) ReceiveShiftReg <= 8'b0;
|
||||||
else ReceiveShiftReg <= {ReceiveShiftReg[6:0], ShiftIn};
|
else ReceiveShiftReg <= {ReceiveShiftReg[6:0], ShiftIn};
|
||||||
end
|
end
|
||||||
|
|
||||||
// Aligns received data and reverses if little-endian
|
// Aligns received data and reverses if little-endian
|
||||||
assign LeftShiftAmount = 4'h8 - Format[4:1];
|
assign LeftShiftAmount = 4'h8 - Format[4:1];
|
||||||
assign ASR = ReceiveShiftReg << LeftShiftAmount[2:0];
|
assign ASR = ReceiveShiftReg << LeftShiftAmount[2:0];
|
||||||
assign ReceiveShiftRegEndian = Format[0] ? {ASR[0], ASR[1], ASR[2], ASR[3], ASR[4], ASR[5], ASR[6], ASR[7]} : ASR[7:0];
|
assign ReceiveShiftRegEndian = Format[0] ? {<<{ASR[7:0]}} : ASR[7:0];
|
||||||
|
|
||||||
// Interrupt logic: raise interrupt if any enabled interrupts are pending
|
// Interrupt logic: raise interrupt if any enabled interrupts are pending
|
||||||
assign SPIIntr = |(InterruptPending & InterruptEnable);
|
assign SPIIntr = |(InterruptPending & InterruptEnable);
|
||||||
|
|
||||||
// Chip select logic
|
// Chip select logic
|
||||||
|
assign ChipSelectInternal = InactiveState ? ChipSelectDef : ~ChipSelectDef;
|
||||||
always_comb
|
always_comb
|
||||||
case(ChipSelectID[1:0])
|
case(ChipSelectID[1:0])
|
||||||
2'b00: ChipSelectAuto = {ChipSelectDef[3], ChipSelectDef[2], ChipSelectDef[1], ChipSelectInternal[0]};
|
2'b00: ChipSelectAuto = {ChipSelectDef[3], ChipSelectDef[2], ChipSelectDef[1], ChipSelectInternal[0]};
|
||||||
@ -462,6 +329,6 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
|
|||||||
2'b10: ChipSelectAuto = {ChipSelectDef[3],ChipSelectInternal[2], ChipSelectDef[1], ChipSelectDef[0]};
|
2'b10: ChipSelectAuto = {ChipSelectDef[3],ChipSelectInternal[2], ChipSelectDef[1], ChipSelectDef[0]};
|
||||||
2'b11: ChipSelectAuto = {ChipSelectInternal[3],ChipSelectDef[2], ChipSelectDef[1], ChipSelectDef[0]};
|
2'b11: ChipSelectAuto = {ChipSelectInternal[3],ChipSelectDef[2], ChipSelectDef[1], ChipSelectDef[0]};
|
||||||
endcase
|
endcase
|
||||||
|
|
||||||
assign SPICS = ChipSelectMode[0] ? ChipSelectDef : ChipSelectAuto;
|
assign SPICS = ChipSelectMode[0] ? ChipSelectDef : ChipSelectAuto;
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
@ -28,21 +28,33 @@
|
|||||||
// and limitations under the License.
|
// and limitations under the License.
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
|
||||||
module spi_controller (
|
module spi_controller (
|
||||||
input logic PCLK,
|
input logic PCLK,
|
||||||
input logic PRESETn,
|
input logic PRESETn,
|
||||||
|
|
||||||
|
// Start Transmission
|
||||||
input logic TransmitStart,
|
input logic TransmitStart,
|
||||||
|
input logic ResetSCLKenable,
|
||||||
|
|
||||||
|
// Registers
|
||||||
input logic [11:0] SckDiv,
|
input logic [11:0] SckDiv,
|
||||||
input logic [1:0] SckMode,
|
input logic [1:0] SckMode,
|
||||||
input logic [1:0] CSMode,
|
input logic [1:0] CSMode,
|
||||||
input logic [15:0] Delay0,
|
input logic [15:0] Delay0,
|
||||||
input logic [15:0] Delay1,
|
input logic [15:0] Delay1,
|
||||||
input logic [7:0] txFIFORead,
|
|
||||||
|
// Is the Transmit FIFO Empty?
|
||||||
input logic txFIFOReadEmpty,
|
input logic txFIFOReadEmpty,
|
||||||
output logic SPICLK,
|
|
||||||
output logic SPIOUT,
|
// Control signals
|
||||||
output logic CS
|
output logic SCLKenable,
|
||||||
|
output logic ShiftEdge,
|
||||||
|
output logic SampleEdge,
|
||||||
|
output logic EndOfFrame,
|
||||||
|
output logic EndOfFrameDelay,
|
||||||
|
output logic Transmitting,
|
||||||
|
output logic InactiveState,
|
||||||
|
output logic SPICLK
|
||||||
);
|
);
|
||||||
|
|
||||||
// CSMode Stuff
|
// CSMode Stuff
|
||||||
@ -55,36 +67,32 @@ module spi_controller (
|
|||||||
|
|
||||||
// SCLKenable stuff
|
// SCLKenable stuff
|
||||||
logic [11:0] DivCounter;
|
logic [11:0] DivCounter;
|
||||||
logic SCLKenable;
|
// logic SCLKenable;
|
||||||
logic SCLKenableEarly;
|
// logic SCLKenableEarly;
|
||||||
logic SCLKenableLate;
|
|
||||||
logic EdgeTiming;
|
|
||||||
logic ZeroDiv;
|
logic ZeroDiv;
|
||||||
logic Clock0;
|
|
||||||
logic Clock1;
|
|
||||||
logic SCK; // SUPER IMPORTANT, THIS CAN'T BE THE SAME AS SPICLK!
|
logic SCK; // SUPER IMPORTANT, THIS CAN'T BE THE SAME AS SPICLK!
|
||||||
|
|
||||||
|
|
||||||
// Shift and Sample Edges
|
// Shift and Sample Edges
|
||||||
logic PreShiftEdge;
|
logic PreShiftEdge;
|
||||||
logic PreSampleEdge;
|
logic PreSampleEdge;
|
||||||
logic ShiftEdge;
|
// logic ShiftEdge;
|
||||||
logic SampleEdge;
|
// logic SampleEdge;
|
||||||
|
|
||||||
// Frame stuff
|
// Frame stuff
|
||||||
logic [2:0] BitNum;
|
logic [2:0] BitNum;
|
||||||
logic LastBit;
|
logic LastBit;
|
||||||
logic EndOfFrame;
|
//logic EndOfFrame;
|
||||||
logic EndOfFrameDelay;
|
//logic EndOfFrameDelay;
|
||||||
logic PhaseOneOffset;
|
logic PhaseOneOffset;
|
||||||
|
|
||||||
// Transmit Stuff
|
// Transmit Stuff
|
||||||
logic ContinueTransmit;
|
logic ContinueTransmit;
|
||||||
|
|
||||||
// SPIOUT Stuff
|
// SPIOUT Stuff
|
||||||
logic TransmitLoad;
|
// logic TransmitLoad;
|
||||||
logic [7:0] TransmitReg;
|
logic [7:0] TransmitReg;
|
||||||
logic Transmitting;
|
//logic Transmitting;
|
||||||
logic EndTransmission;
|
logic EndTransmission;
|
||||||
|
|
||||||
logic HoldMode;
|
logic HoldMode;
|
||||||
@ -135,13 +143,9 @@ module spi_controller (
|
|||||||
// SampleEdge. This makes sure that SPICLK is an output of a register
|
// SampleEdge. This makes sure that SPICLK is an output of a register
|
||||||
// and it properly synchronizes signals.
|
// and it properly synchronizes signals.
|
||||||
|
|
||||||
assign SCLKenableLate = DivCounter > SckDiv;
|
|
||||||
assign SCLKenable = DivCounter == SckDiv;
|
assign SCLKenable = DivCounter == SckDiv;
|
||||||
assign SCLKenableEarly = (DivCounter + 1'b1) == SckDiv;
|
// assign SCLKenableEarly = (DivCounter + 1'b1) == SckDiv;
|
||||||
assign LastBit = BitNum == 3'd7;
|
assign LastBit = BitNum == 3'd7;
|
||||||
assign EdgeTiming = SckDiv > 12'b0 ? SCLKenableEarly : SCLKenable;
|
|
||||||
|
|
||||||
//assign SPICLK = Clock0;
|
|
||||||
|
|
||||||
assign ContinueTransmit = ~txFIFOReadEmpty & EndOfFrame;
|
assign ContinueTransmit = ~txFIFOReadEmpty & EndOfFrame;
|
||||||
assign EndTransmission = txFIFOReadEmpty & EndOfFrameDelay;
|
assign EndTransmission = txFIFOReadEmpty & EndOfFrameDelay;
|
||||||
@ -196,7 +200,7 @@ module spi_controller (
|
|||||||
end
|
end
|
||||||
|
|
||||||
// Reset divider
|
// Reset divider
|
||||||
if (SCLKenable | TransmitStart) begin
|
if (SCLKenable | TransmitStart | ResetSCLKenable) begin
|
||||||
DivCounter <= 12'b0;
|
DivCounter <= 12'b0;
|
||||||
end else begin
|
end else begin
|
||||||
DivCounter = DivCounter + 12'd1;
|
DivCounter = DivCounter + 12'd1;
|
||||||
@ -242,8 +246,8 @@ module spi_controller (
|
|||||||
// typedef enum logic [2:0] {INACTIVE, CSSCK, TRANSMIT, SCKCS, HOLD, INTERCS, INTERXFR} statetype;
|
// typedef enum logic [2:0] {INACTIVE, CSSCK, TRANSMIT, SCKCS, HOLD, INTERCS, INTERXFR} statetype;
|
||||||
// statetype CurrState, NextState;
|
// statetype CurrState, NextState;
|
||||||
|
|
||||||
assign HoldMode = CSMode == 2'b10;
|
assign HoldMode = CSMode == HOLDMODE;
|
||||||
assign TransmitLoad = TransmitStart | (EndOfFrameDelay & ~txFIFOReadEmpty);
|
// assign TransmitLoad = TransmitStart | (EndOfFrameDelay & ~txFIFOReadEmpty);
|
||||||
|
|
||||||
always_ff @(posedge PCLK) begin
|
always_ff @(posedge PCLK) begin
|
||||||
if (~PRESETn) begin
|
if (~PRESETn) begin
|
||||||
@ -255,61 +259,43 @@ module spi_controller (
|
|||||||
|
|
||||||
always_comb begin
|
always_comb begin
|
||||||
case (CurrState)
|
case (CurrState)
|
||||||
INACTIVE: begin // INACTIVE case --------------------------------
|
INACTIVE: if (TransmitStart)
|
||||||
if (TransmitStart) begin
|
if (~HasCSSCK) NextState = TRANSMIT;
|
||||||
if (~HasCSSCK) begin
|
else NextState = CSSCK;
|
||||||
NextState = TRANSMIT;
|
else NextState = INACTIVE;
|
||||||
end else begin
|
CSSCK: if (EndOfCSSCK) NextState = TRANSMIT;
|
||||||
NextState = CSSCK;
|
else NextState = CSSCK;
|
||||||
end
|
|
||||||
end else begin
|
|
||||||
NextState = INACTIVE;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
CSSCK: begin // DELAY0 case -------------------------------------
|
|
||||||
if (EndOfCSSCK) begin
|
|
||||||
NextState = TRANSMIT;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
TRANSMIT: begin // TRANSMIT case --------------------------------
|
TRANSMIT: begin // TRANSMIT case --------------------------------
|
||||||
case(CSMode)
|
case(CSMode)
|
||||||
AUTOMODE: begin
|
AUTOMODE: begin
|
||||||
if (EndTransmission) begin
|
if (EndTransmission) NextState = INACTIVE;
|
||||||
NextState = INACTIVE;
|
else if (ContinueTransmit) NextState = SCKCS;
|
||||||
end else if (ContinueTransmit) begin
|
|
||||||
NextState = SCKCS;
|
|
||||||
end
|
|
||||||
end
|
end
|
||||||
HOLDMODE: begin
|
HOLDMODE: begin
|
||||||
if (EndTransmission) begin
|
if (EndTransmission) NextState = HOLD;
|
||||||
NextState = HOLD;
|
else if (ContinueTransmit & HasINTERXFR) NextState = INTERXFR;
|
||||||
end else if (ContinueTransmit) begin
|
else NextState = TRANSMIT;
|
||||||
if (HasINTERXFR) NextState = INTERXFR;
|
|
||||||
end
|
|
||||||
end
|
end
|
||||||
OFFMODE: begin
|
OFFMODE: begin
|
||||||
|
|
||||||
end
|
end
|
||||||
|
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
SCKCS: begin // SCKCS case --------------------------------------
|
SCKCS: begin // SCKCS case --------------------------------------
|
||||||
if (EndOfSCKCS) begin
|
if (EndOfSCKCS)
|
||||||
if (EndTransmission) begin
|
if (EndTransmission)
|
||||||
if (CSMode == AUTOMODE) NextState = INACTIVE;
|
if (CSMode == AUTOMODE) NextState = INACTIVE;
|
||||||
else if (CSMode == HOLDMODE) NextState = HOLD;
|
else if (CSMode == HOLDMODE) NextState = HOLD;
|
||||||
end else if (ContinueTransmit) begin
|
else if (ContinueTransmit)
|
||||||
if (HasINTERCS) NextState = INTERCS;
|
if (HasINTERCS) NextState = INTERCS;
|
||||||
else NextState = TRANSMIT;
|
else NextState = TRANSMIT;
|
||||||
end
|
end
|
||||||
end
|
|
||||||
end
|
|
||||||
HOLD: begin // HOLD mode case -----------------------------------
|
HOLD: begin // HOLD mode case -----------------------------------
|
||||||
if (CSMode == AUTOMODE) begin
|
if (CSMode == AUTOMODE) begin
|
||||||
NextState = INACTIVE;
|
NextState = INACTIVE;
|
||||||
end else if (TransmitStart) begin // If FIFO is written to, start again.
|
end else if (TransmitStart) begin // If FIFO is written to, start again.
|
||||||
NextState = TRANSMIT;
|
NextState = TRANSMIT;
|
||||||
end
|
end else NextState = HOLD;
|
||||||
end
|
end
|
||||||
INTERCS: begin // INTERCS case ----------------------------------
|
INTERCS: begin // INTERCS case ----------------------------------
|
||||||
if (EndOfINTERCS) begin
|
if (EndOfINTERCS) begin
|
||||||
@ -330,19 +316,6 @@ module spi_controller (
|
|||||||
|
|
||||||
assign Transmitting = CurrState == TRANSMIT;
|
assign Transmitting = CurrState == TRANSMIT;
|
||||||
assign DelayIsNext = (NextState == CSSCK | NextState == SCKCS | NextState == INTERCS | NextState == INTERXFR);
|
assign DelayIsNext = (NextState == CSSCK | NextState == SCKCS | NextState == INTERCS | NextState == INTERXFR);
|
||||||
|
assign InactiveState = CurrState == INACTIVE | CurrState == INTERCS;
|
||||||
//
|
|
||||||
always_ff @(posedge PCLK) begin
|
|
||||||
if (~PRESETn) begin
|
|
||||||
TransmitReg <= 8'b0;
|
|
||||||
end else if (TransmitLoad) begin
|
|
||||||
TransmitReg <= txFIFORead;
|
|
||||||
end else if (ShiftEdge) begin
|
|
||||||
TransmitReg <= {TransmitReg[6:0], TransmitReg[0]};
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
assign SPIOUT = TransmitReg[7];
|
|
||||||
assign CS = CurrState == INACTIVE | CurrState == INTERCS;
|
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
Loading…
Reference in New Issue
Block a user