mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Cleaned up consolidated arch_b tests from tests.vh
This commit is contained in:
Kip Macsai-Goren
parent
f8f89e692e
commit
b658329118
@ -109,7 +109,6 @@ logic [3:0] dummy;
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"arch64zbb": if (`ZBB_SUPPORTED) tests = arch64zbb;
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"arch64zbb": if (`ZBB_SUPPORTED) tests = arch64zbb;
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"arch64zbc": if (`ZBC_SUPPORTED) tests = arch64zbc;
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"arch64zbc": if (`ZBC_SUPPORTED) tests = arch64zbc;
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"arch64zbs": if (`ZBS_SUPPORTED) tests = arch64zbs;
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"arch64zbs": if (`ZBS_SUPPORTED) tests = arch64zbs;
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"arch64b": if (`ZBB_SUPPORTED & `ZBA_SUPPORTED & `ZBS_SUPPORTED & `ZBC_SUPPORTED) tests = arch64b;
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endcase
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endcase
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end else begin // RV32
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end else begin // RV32
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case (TEST)
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case (TEST)
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@ -138,7 +137,6 @@ logic [3:0] dummy;
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"arch32zbb": if (`ZBB_SUPPORTED) tests = arch32zbb;
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"arch32zbb": if (`ZBB_SUPPORTED) tests = arch32zbb;
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"arch32zbc": if (`ZBC_SUPPORTED) tests = arch32zbc;
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"arch32zbc": if (`ZBC_SUPPORTED) tests = arch32zbc;
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"arch32zbs": if (`ZBS_SUPPORTED) tests = arch32zbs;
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"arch32zbs": if (`ZBS_SUPPORTED) tests = arch32zbs;
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"arch32b": if (`ZBB_SUPPORTED & `ZBA_SUPPORTED & `ZBS_SUPPORTED & `ZBC_SUPPORTED) tests = arch32b;
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endcase
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endcase
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end
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end
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if (tests.size() == 0) begin
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if (tests.size() == 0) begin
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@ -364,7 +362,7 @@ logic [3:0] dummy;
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errors = errors+1;
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errors = errors+1;
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$display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h",
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$display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h",
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tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
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tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
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$stop;//***debug
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//$stop;//***debug
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end
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end
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i = i + 1;
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i = i + 1;
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end
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end
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@ -929,80 +929,6 @@ string imperas32f[] = '{
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"rv32i_m/B/src/bseti-01.S"
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"rv32i_m/B/src/bseti-01.S"
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};
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};
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string arch32b[] = '{
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`RISCVARCHTEST,
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"rv32i_m/B/src/clmul-01.S",
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"rv32i_m/B/src/clmulh-01.S",
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"rv32i_m/B/src/clmulr-01.S",
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"rv32i_m/B/src/bclr-01.S",
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"rv32i_m/B/src/bclri-01.S",
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"rv32i_m/B/src/bext-01.S",
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"rv32i_m/B/src/bexti-01.S",
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"rv32i_m/B/src/binv-01.S",
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"rv32i_m/B/src/binvi-01.S",
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"rv32i_m/B/src/bset-01.S",
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"rv32i_m/B/src/bseti-01.S",
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"rv32i_m/B/src/max-01.S",
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"rv32i_m/B/src/maxu-01.S",
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"rv32i_m/B/src/min-01.S",
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"rv32i_m/B/src/minu-01.S",
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"rv32i_m/B/src/orcb_32-01.S",
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"rv32i_m/B/src/rev8_32-01.S",
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"rv32i_m/B/src/andn-01.S",
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"rv32i_m/B/src/orn-01.S",
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"rv32i_m/B/src/xnor-01.S",
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"rv32i_m/B/src/zext.h_32-01.S",
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"rv32i_m/B/src/sext.b-01.S",
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"rv32i_m/B/src/sext.h-01.S",
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"rv32i_m/B/src/clz-01.S",
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"rv32i_m/B/src/cpop-01.S",
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"rv32i_m/B/src/ctz-01.S",
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"rv32i_m/B/src/ror-01.S",
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"rv32i_m/B/src/rori-01.S",
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"rv32i_m/B/src/rol-01.S",
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"rv32i_m/B/src/sh1add-01.S",
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"rv32i_m/B/src/sh2add-01.S",
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"rv32i_m/B/src/sh3add-01.S",
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"rv32i_m/I/src/add-01.S",
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"rv32i_m/I/src/addi-01.S",
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"rv32i_m/I/src/and-01.S",
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"rv32i_m/I/src/andi-01.S",
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"rv32i_m/I/src/auipc-01.S",
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"rv32i_m/I/src/beq-01.S",
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"rv32i_m/I/src/bge-01.S",
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"rv32i_m/I/src/bgeu-01.S",
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"rv32i_m/I/src/blt-01.S",
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"rv32i_m/I/src/bltu-01.S",
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"rv32i_m/I/src/bne-01.S",
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"rv32i_m/I/src/fence-01.S",
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"rv32i_m/I/src/jal-01.S",
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"rv32i_m/I/src/jalr-01.S",
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"rv32i_m/I/src/lb-align-01.S",
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"rv32i_m/I/src/lbu-align-01.S",
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"rv32i_m/I/src/lh-align-01.S",
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"rv32i_m/I/src/lhu-align-01.S",
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"rv32i_m/I/src/lui-01.S",
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"rv32i_m/I/src/lw-align-01.S",
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"rv32i_m/I/src/or-01.S",
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"rv32i_m/I/src/ori-01.S",
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"rv32i_m/I/src/sb-align-01.S",
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"rv32i_m/I/src/sh-align-01.S",
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"rv32i_m/I/src/sll-01.S",
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"rv32i_m/I/src/slli-01.S",
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"rv32i_m/I/src/slt-01.S",
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"rv32i_m/I/src/slti-01.S",
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"rv32i_m/I/src/sltiu-01.S",
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"rv32i_m/I/src/sltu-01.S",
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"rv32i_m/I/src/sra-01.S",
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"rv32i_m/I/src/srai-01.S",
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"rv32i_m/I/src/srl-01.S",
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"rv32i_m/I/src/srli-01.S",
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"rv32i_m/I/src/sub-01.S",
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"rv32i_m/I/src/sw-align-01.S",
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"rv32i_m/I/src/xor-01.S",
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"rv32i_m/I/src/xori-01.S"
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};
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string arch64m[] = '{
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string arch64m[] = '{
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`RISCVARCHTEST,
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`RISCVARCHTEST,
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"rv64i_m/M/src/div-01.S",
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"rv64i_m/M/src/div-01.S",
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@ -1440,104 +1366,6 @@ string imperas32f[] = '{
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"rv64i_m/D/src/fssub.d_b8-01.S"
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"rv64i_m/D/src/fssub.d_b8-01.S"
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};
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};
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string arch64b[] = '{
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`RISCVARCHTEST,
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"rv64i_m/B/src/max-01.S",
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"rv64i_m/B/src/maxu-01.S",
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"rv64i_m/B/src/min-01.S",
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"rv64i_m/B/src/minu-01.S",
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"rv64i_m/B/src/orcb_64-01.S",
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"rv64i_m/B/src/rev8-01.S",
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"rv64i_m/B/src/andn-01.S",
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"rv64i_m/B/src/orn-01.S",
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"rv64i_m/B/src/xnor-01.S",
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"rv64i_m/B/src/zext.h-01.S",
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"rv64i_m/B/src/sext.b-01.S",
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"rv64i_m/B/src/sext.h-01.S",
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"rv64i_m/B/src/clz-01.S",
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"rv64i_m/B/src/clzw-01.S",
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"rv64i_m/B/src/cpop-01.S",
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"rv64i_m/B/src/cpopw-01.S",
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"rv64i_m/B/src/ctz-01.S",
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"rv64i_m/B/src/ctzw-01.S",
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"rv64i_m/B/src/rolw-01.S",
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"rv64i_m/B/src/ror-01.S",
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"rv64i_m/B/src/rori-01.S",
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"rv64i_m/B/src/roriw-01.S",
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"rv64i_m/B/src/rorw-01.S",
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"rv64i_m/B/src/rol-01.S",
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"rv64i_m/B/src/slli.uw-01.S",
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"rv64i_m/B/src/add.uw-01.S",
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"rv64i_m/B/src/sh1add-01.S",
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"rv64i_m/B/src/sh2add-01.S",
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"rv64i_m/B/src/sh3add-01.S",
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"rv64i_m/B/src/sh1add.uw-01.S",
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"rv64i_m/B/src/sh2add.uw-01.S",
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"rv64i_m/B/src/sh3add.uw-01.S",
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"rv64i_m/I/src/add-01.S",
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"rv64i_m/I/src/addi-01.S",
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"rv64i_m/I/src/addiw-01.S",
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"rv64i_m/I/src/addw-01.S",
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"rv64i_m/I/src/and-01.S",
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"rv64i_m/I/src/andi-01.S",
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"rv64i_m/I/src/auipc-01.S",
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"rv64i_m/I/src/beq-01.S",
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"rv64i_m/I/src/bge-01.S",
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"rv64i_m/I/src/bgeu-01.S",
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"rv64i_m/I/src/blt-01.S",
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"rv64i_m/I/src/bltu-01.S",
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"rv64i_m/I/src/bne-01.S",
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"rv64i_m/I/src/fence-01.S",
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"rv64i_m/I/src/jal-01.S",
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"rv64i_m/I/src/jalr-01.S",
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"rv64i_m/I/src/lb-align-01.S",
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"rv64i_m/I/src/lbu-align-01.S",
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"rv64i_m/I/src/ld-align-01.S",
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"rv64i_m/I/src/lh-align-01.S",
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"rv64i_m/I/src/lhu-align-01.S",
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"rv64i_m/I/src/lui-01.S",
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"rv64i_m/I/src/lw-align-01.S",
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"rv64i_m/I/src/lwu-align-01.S",
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"rv64i_m/I/src/or-01.S",
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"rv64i_m/I/src/ori-01.S",
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"rv64i_m/I/src/sb-align-01.S",
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"rv64i_m/I/src/sd-align-01.S",
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"rv64i_m/I/src/sh-align-01.S",
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"rv64i_m/I/src/sll-01.S",
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"rv64i_m/I/src/slli-01.S",
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"rv64i_m/I/src/slliw-01.S",
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"rv64i_m/I/src/sllw-01.S",
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"rv64i_m/I/src/slt-01.S",
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"rv64i_m/I/src/slti-01.S",
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"rv64i_m/I/src/sltiu-01.S",
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"rv64i_m/I/src/sltu-01.S",
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"rv64i_m/I/src/sra-01.S",
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"rv64i_m/I/src/srai-01.S",
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"rv64i_m/I/src/sraiw-01.S",
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"rv64i_m/I/src/sraw-01.S",
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"rv64i_m/I/src/srl-01.S",
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"rv64i_m/I/src/srli-01.S",
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"rv64i_m/I/src/srliw-01.S",
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"rv64i_m/I/src/srlw-01.S",
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"rv64i_m/I/src/sub-01.S",
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"rv64i_m/I/src/subw-01.S",
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"rv64i_m/I/src/sw-align-01.S",
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"rv64i_m/I/src/xor-01.S",
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"rv64i_m/I/src/xori-01.S",
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"rv64i_m/B/src/clmul-01.S",
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"rv64i_m/B/src/clmulh-01.S",
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"rv64i_m/B/src/clmulr-01.S",
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"rv64i_m/B/src/bclr-01.S",
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"rv64i_m/B/src/bclri-01.S",
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"rv64i_m/B/src/bext-01.S",
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"rv64i_m/B/src/bexti-01.S",
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"rv64i_m/B/src/binv-01.S",
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"rv64i_m/B/src/binvi-01.S",
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"rv64i_m/B/src/bset-01.S",
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"rv64i_m/B/src/bseti-01.S"
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};
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string arch64zba[] = '{
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string arch64zba[] = '{
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`RISCVARCHTEST,
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`RISCVARCHTEST,
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"rv64i_m/B/src/slli.uw-01.S",
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"rv64i_m/B/src/slli.uw-01.S",
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@ -1550,8 +1378,6 @@ string arch64b[] = '{
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"rv64i_m/B/src/sh3add.uw-01.S"
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"rv64i_m/B/src/sh3add.uw-01.S"
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};
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};
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string arch64zbb[] = '{
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string arch64zbb[] = '{
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`RISCVARCHTEST,
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`RISCVARCHTEST,
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"rv64i_m/B/src/max-01.S",
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"rv64i_m/B/src/max-01.S",
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@ -1599,8 +1425,6 @@ string arch64zbs[] = '{
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"rv64i_m/B/src/bseti-01.S"
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"rv64i_m/B/src/bseti-01.S"
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};
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};
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string arch32priv[] = '{
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string arch32priv[] = '{
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`RISCVARCHTEST,
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`RISCVARCHTEST,
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"rv32i_m/privilege/src/ebreak.S",
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"rv32i_m/privilege/src/ebreak.S",
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