From b61d881c1bb9f816886f5c2fe2ab2787c37cdd8e Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Tue, 28 Feb 2023 11:54:10 -0800 Subject: [PATCH] added BRegWrite, BW64, BALUOp signals to bctrl and controller -TODO: Main decode in bmuctrl must assert these 3 signals --- src/ieu/bmu/bmuctrl.sv | 11 +++++++---- src/ieu/controller.sv | 5 ++++- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 097ee27e8..0ca949efb 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -38,6 +38,9 @@ module bmuctrl( output logic [2:0] ALUSelectD, // ALU Mux select signal output logic [3:0] BSelectD, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding in Decode stage output logic [2:0] ZBBSelectD, // ZBB mux select signal in Decode stage NOTE: do we need this in decode? + output logic BRegWriteD, // Indicates if it is a R type B instruction + output logic BW64D, // Indiciates if it is a W type B instruction + output logic BALUOpD, // Indicates if it is an ALU B instruction // Execute stage control signals input logic StallE, FlushE, // Stall, flush Execute stage output logic [2:0] ALUSelectE, @@ -50,7 +53,7 @@ module bmuctrl( logic [6:0] Funct7D; // Funct7 field in Decode stage logic [4:0] Rs2D; // Rs2 source register in Decode stage - `define BMUCTRLW 10 + `define BMUCTRLW 13 logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals @@ -64,7 +67,7 @@ module bmuctrl( // Main Instruction Decoder always_comb casez({OpD, Funct7D, Funct3D}) - // ALUSelect_BSelect_ZBBSelect + // ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp // ZBS 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000; // bclri 17'b0010011_0100101_001: if (`XLEN == 64) @@ -146,12 +149,12 @@ module bmuctrl( 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0100_110; // min 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0100_110; // minu - default: BMUControlsD = {Funct3D, {7'b0}}; // not B instruction or shift + default: BMUControlsD = {Funct3D, {10'b0}}; // not B instruction or shift endcase // Unpack Control Signals - assign {ALUSelectD,BSelectD,ZBBSelectD} = BMUControlsD; + assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD, BW64D, BALUOpD} = BMUControlsD; diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 2520bbe2d..e39c5cacf 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -121,6 +121,9 @@ module controller( logic IntDivM; // Integer divide instruction logic [3:0] BSelectD; // One-Hot encoding if it's ZBA_ZBB_ZBC_ZBS instruction in decode stage logic [2:0] ZBBSelectD; // ZBB Mux Select Signal + logic BRegWriteD; // Indicates if it is a R type B instruction in decode stage + logic BW64D; // Indiciates if it is a W type B instruction in decode stage + logic BALUOpD; // Indicates if it is an ALU B instruction in decode stage // Extract fields @@ -241,7 +244,7 @@ module controller( assign ALUControlD = {W64D, SubArithD, ALUOpD}; if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags - bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE); + bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, BW64D, BALUOpD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE); end else begin: bitmanipi assign ALUSelectD = Funct3D; assign ALUSelectE = Funct3E;