From 1bd6351e1fd4b0f2ad0e248cd7999d2e098ba189 Mon Sep 17 00:00:00 2001
From: Katherine Parry <kparry4@gmail.com>
Date: Fri, 29 Jul 2022 22:54:49 +0000
Subject: [PATCH 1/2] re-added FStore2 in Cache

---
 pipelined/src/cache/cache.sv | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv
index d28697e21..609810e8c 100644
--- a/pipelined/src/cache/cache.sv
+++ b/pipelined/src/cache/cache.sv
@@ -162,12 +162,18 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGWPL, WORDLEN, MUXINTER
   logic [LINELEN-1:0] FinalWriteDataDup;
   assign FinalWriteDataDup = {WORDSPERLINE{FinalWriteData}};
 
-  onehotdecoder #(LOGWPL) adrdec(
-    .bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecoded));
+  if(`LLEN>`XLEN)begin 
+    logic [2**LOGWPL-1:0] MemPAdrDecodedtmp;
+    onehotdecoder #(LOGWPL) adrdec(
+      .bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecodedtmp));
+    assign MemPAdrDecoded = MemPAdrDecodedtmp|{MemPAdrDecodedtmp[2**LOGWPL-2:0]&{2**LOGWPL-1{FStore2}}, 1'b0};
+  end else
+    onehotdecoder #(LOGWPL) adrdec(
+      .bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecoded));
   for(index = 0; index < 2**LOGWPL; index++) begin
     assign DemuxedByteMask[(index+1)*(`XLEN/8)-1:index*(`XLEN/8)] = MemPAdrDecoded[index] ? ByteMask : '0;
   end
-  // *** have to add back in fstore2
+  
   assign LineByteMux = SetValid & ~SetDirty ? '1 : ~DemuxedByteMask;  // If load miss set all muxes to 1.
   assign LineByteMask = ~SetValid & ~SetDirty ? '0 : ~SetValid & SetDirty ? DemuxedByteMask : '1; // if store hit only enable the word and subword bytes, else write all bytes.
 

From 8ff3a693af891c99945ebac02205a2da7bb92ba5 Mon Sep 17 00:00:00 2001
From: Katherine Parry <kparry4@gmail.com>
Date: Mon, 1 Aug 2022 19:56:25 +0000
Subject: [PATCH 2/2] regression passes fpu tests

---
 pipelined/src/fpu/fpu.sv | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv
index d98079b2e..4b7a1ffea 100755
--- a/pipelined/src/fpu/fpu.sv
+++ b/pipelined/src/fpu/fpu.sv
@@ -319,10 +319,23 @@ module fpu (
    assign PreNVE = CmpNVE&(OpCtrlE[2]|FWriteIntE);
 
    // select the result that may be written to the integer register - to IEU
+   
+   logic [`FLEN-1:0] SgnExtXE;
+   generate
+   if(`FPSIZES == 1)
+      assign SgnExtXE = XE;
+   else if(`FPSIZES == 2) 
+      mux2 #(`FLEN) sgnextmux ({{`FLEN-`LEN1{XsE}}, XE[`LEN1-1:0]}, XE, FmtE, SgnExtXE);
+   else if(`FPSIZES == 3 | `FPSIZES == 4)
+      mux4 #(`FLEN) fmulzeromux ({{`FLEN-`H_LEN{XsE}}, XE[`H_LEN-1:0]}, 
+                                 {{`FLEN-`S_LEN{XsE}}, XE[`S_LEN-1:0]}, 
+                                 {{`FLEN-`D_LEN{XsE}}, XE[`D_LEN-1:0]}, 
+                                 XE, FmtE, SgnExtXE); // NaN boxing zeroes
+   endgenerate
    if (`FLEN>`XLEN)
-      assign IntSrcXE = XE[`XLEN-1:0];
+      assign IntSrcXE = SgnExtXE[`XLEN-1:0];
    else 
-      assign IntSrcXE = {{`XLEN-`FLEN{XE[`FLEN-1:0]}}, XE};
+      assign IntSrcXE = {{`XLEN-`FLEN{XsE}}, SgnExtXE};
 
    mux3 #(`XLEN) IntResMux (ClassResE, IntSrcXE, CmpIntResE, {~FResSelE[1], FResSelE[0]}, FIntResE);
    // *** DH 5/25/22: CvtRes will move to mem stage.  Premux in execute to save area, then make sure stalls are ok