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fix buildroot checkpointing and add it back to regression

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bbracker 2022-03-02 16:00:19 +00:00
parent 29179c6787
commit b6031bb15f
2 changed files with 7 additions and 4 deletions
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2
pipelined/regression/regression-wally
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@ -60,7 +60,7 @@ tc = TestCase(
variant="rv64gc", variant="rv64gc",
cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do buildroot buildroot-checkpoint $RISCV 400100000 400000001 400000000\n!", # *** will this work with rv64gc rather than buildroot config? cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do buildroot buildroot-checkpoint $RISCV 400100000 400000001 400000000\n!", # *** will this work with rv64gc rather than buildroot config?
grepstr="400100000 instructions") grepstr="400100000 instructions")
#configs.append(tc) #temporarily removed until I make this checkpoint configs.append(tc)
tests64gc = ["arch64i", "arch64priv", "arch64c", "arch64m", "arch64d", "imperas64i", "imperas64f", "imperas64d", "imperas64m", "wally64a", "imperas64c", "wally64priv"] # , "imperas64mmu" "wally64i", #, "testsBP64"] tests64gc = ["arch64i", "arch64priv", "arch64c", "arch64m", "arch64d", "imperas64i", "imperas64f", "imperas64d", "imperas64m", "wally64a", "imperas64c", "wally64priv"] # , "imperas64mmu" "wally64i", #, "testsBP64"]
for test in tests64gc: for test in tests64gc:

7
pipelined/testbench/testbench-linux.sv
View File

@ -310,6 +310,8 @@ module testbench;
force dut.core.priv.priv.ExtIntM = 0; force dut.core.priv.priv.ExtIntM = 0;
$sformat(testvectorDir,"%s/linux-testvectors/",RISCV_DIR); $sformat(testvectorDir,"%s/linux-testvectors/",RISCV_DIR);
$sformat(linuxImageDir,"%s/buildroot/output/images/",RISCV_DIR); $sformat(linuxImageDir,"%s/buildroot/output/images/",RISCV_DIR);
if (CHECKPOINT!=0)
$sformat(checkpointDir,"%s/linux-testvectors/checkpoint%0d/",RISCV_DIR,CHECKPOINT);
$readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem); $readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
$readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem); $readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem);
ProgramAddrMapFile = {linuxImageDir,"vmlinux.objdump.addr"}; ProgramAddrMapFile = {linuxImageDir,"vmlinux.objdump.addr"};
@ -319,7 +321,10 @@ module testbench;
readResult = $fread(dut.uncore.bootrom.bootrom.RAM,memFile); readResult = $fread(dut.uncore.bootrom.bootrom.RAM,memFile);
$fclose(memFile); $fclose(memFile);
// initialize RAM // initialize RAM
if (CHECKPOINT==0)
memFile = $fopen({testvectorDir,"ram.bin"}, "rb"); memFile = $fopen({testvectorDir,"ram.bin"}, "rb");
else
memFile = $fopen({checkpointDir,"ram.bin"}, "rb");
readResult = $fread(dut.uncore.ram.ram.RAM,memFile); readResult = $fread(dut.uncore.ram.ram.RAM,memFile);
$fclose(memFile); $fclose(memFile);
if (CHECKPOINT==0) begin // normal if (CHECKPOINT==0) begin // normal
@ -327,8 +332,6 @@ module testbench;
traceFileE = $fopen({testvectorDir,"all.txt"}, "r"); traceFileE = $fopen({testvectorDir,"all.txt"}, "r");
InstrCountW = '0; InstrCountW = '0;
end else begin // checkpoint end else begin // checkpoint
$sformat(checkpointDir,"checkpoint%0d/",CHECKPOINT);
checkpointDir = {testvectorDir,checkpointDir};
//$readmemh({checkpointDir,"ram.txt"}, dut.uncore.ram.ram.RAM); //$readmemh({checkpointDir,"ram.txt"}, dut.uncore.ram.ram.RAM);
traceFileE = $fopen({checkpointDir,"all.txt"}, "r"); traceFileE = $fopen({checkpointDir,"all.txt"}, "r");
traceFileM = $fopen({checkpointDir,"all.txt"}, "r"); traceFileM = $fopen({checkpointDir,"all.txt"}, "r");