From 9a76af809aa1732552e6c289b0ede261d7c9256c Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 14 Oct 2024 15:28:28 -0700 Subject: [PATCH 1/9] Documented ecall services in WALLY-init-lib --- tests/coverage/WALLY-init-lib.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tests/coverage/WALLY-init-lib.h b/tests/coverage/WALLY-init-lib.h index 7e2aee771..3a40d8351 100644 --- a/tests/coverage/WALLY-init-lib.h +++ b/tests/coverage/WALLY-init-lib.h @@ -28,6 +28,12 @@ // The PMP tests are sensitive to the exact addresses in this code, so unfortunately // modifying anything breaks those tests. +// Provides simple firmware services through ecall. Place argument in a0 and issue ecall: +// 0: change to user mode +// 1: change to supervisor mode +// 3: change to machine mode +// 4: terminate program + .section .text.init .global rvtest_entry_point From de8a707361c1049c38b7f8c6461b4d483b92bda9 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 14 Oct 2024 15:28:56 -0700 Subject: [PATCH 2/9] Updated WARL field in senvcfg.CBIE to match ImperasDV --- src/privileged/csrs.sv | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv index 4797f800b..a2a21c2ee 100644 --- a/src/privileged/csrs.sv +++ b/src/privileged/csrs.sv @@ -128,13 +128,16 @@ module csrs import cvw::*; #(parameter cvw_t P) ( else assign STimerInt = 1'b0; + logic [1:0] LegalizedCBIE; + assign LegalizedCBIE = CSRWriteValM[5:4] == 2'b10 ? SENVCFG_REGW[5:4] : CSRWriteValM[5:4]; // Assume WARL for reserved CBIE = 10, keeps old value assign SENVCFG_WriteValM = { {(P.XLEN-8){1'b0}}, CSRWriteValM[7] & P.ZICBOZ_SUPPORTED, - CSRWriteValM[6:4] & {3{P.ZICBOM_SUPPORTED}}, + CSRWriteValM[6] & P.ZICBOM_SUPPORTED, + LegalizedCBIE & {2{P.ZICBOM_SUPPORTED}}, 3'b0, CSRWriteValM[0] & P.VIRTMEM_SUPPORTED - }; + }; flopenr #(P.XLEN) SENVCFGreg(clk, reset, WriteSENVCFGM, SENVCFG_WriteValM, SENVCFG_REGW); From 150641e5d329412626ad418fad1557c021d89578 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 15 Oct 2024 09:08:25 -0700 Subject: [PATCH 3/9] Implemented mhpmevent[3:31] as read-only zero rather than illegal --- src/privileged/csrc.sv | 66 ++++++++++++++++++++++-------------------- 1 file changed, 35 insertions(+), 31 deletions(-) diff --git a/src/privileged/csrc.sv b/src/privileged/csrc.sv index 848cb7e01..8b292513b 100644 --- a/src/privileged/csrc.sv +++ b/src/privileged/csrc.sv @@ -8,7 +8,6 @@ // See RISC-V Privileged Mode Specification 20190608 3.1.10-11 // // Documentation: RISC-V System on Chip Design -// MHPMEVENT is not supported // // A component of the CORE-V-WALLY configurable RISC-V project. // https://github.com/openhwgroup/cvw @@ -66,7 +65,8 @@ module csrc import cvw::*; #(parameter cvw_t P) ( localparam MTIME = 12'hB01; // this is a memory-mapped register; no such CSR exists, and access should faul; localparam MHPMCOUNTERHBASE = 12'hB80; localparam MTIMEH = 12'hB81; // this is a memory-mapped register; no such CSR exists, and access should fault - localparam MHPMEVENTBASE = 12'h320; + localparam MHPMEVENTBASE = 12'h323; + localparam MHPMEVENTLAST = 12'h33F; localparam HPMCOUNTERBASE = 12'hC00; localparam HPMCOUNTERHBASE = 12'hC80; localparam TIME = 12'hC01; @@ -156,37 +156,41 @@ module csrc import cvw::*; #(parameter cvw_t P) ( if (PrivilegeModeW == P.M_MODE | MCOUNTEREN_REGW[CounterNumM] & (!P.S_SUPPORTED | PrivilegeModeW == P.S_MODE | SCOUNTEREN_REGW[CounterNumM])) begin IllegalCSRCAccessM = 1'b0; - if (P.XLEN==64) begin // 64-bit counter reads - // Veri lator doesn't realize this only occurs for XLEN=64 - /* verilator lint_off WIDTH */ - if (CSRAdrM == TIME & ~CSRWriteM) CSRCReadValM = MTIME_CLINT; // TIME register is a shadow of the memory-mapped MTIME from the CLINT - /* verilator lint_on WIDTH */ - else if (CSRAdrM >= MHPMCOUNTERBASE & CSRAdrM < MHPMCOUNTERBASE+P.COUNTERS & CSRAdrM != MTIME) - CSRCReadValM = HPMCOUNTER_REGW[CounterNumM]; - else if (CSRAdrM >= HPMCOUNTERBASE & CSRAdrM < HPMCOUNTERBASE+P.COUNTERS & ~CSRWriteM) // read-only - CSRCReadValM = HPMCOUNTER_REGW[CounterNumM]; - else begin + if (CSRAdrM >= MHPMEVENTBASE & CSRAdrM <= MHPMEVENTLAST) begin + CSRCReadValM = '0; // mphmevent[3:31] tied to read-only zero + end else begin + if (P.XLEN==64) begin // 64-bit counter reads + // Veri lator doesn't realize this only occurs for XLEN=64 + /* verilator lint_off WIDTH */ + if (CSRAdrM == TIME & ~CSRWriteM) CSRCReadValM = MTIME_CLINT; // TIME register is a shadow of the memory-mapped MTIME from the CLINT + /* verilator lint_on WIDTH */ + else if (CSRAdrM >= MHPMCOUNTERBASE & CSRAdrM < MHPMCOUNTERBASE+P.COUNTERS & CSRAdrM != MTIME) + CSRCReadValM = HPMCOUNTER_REGW[CounterNumM]; + else if (CSRAdrM >= HPMCOUNTERBASE & CSRAdrM < HPMCOUNTERBASE+P.COUNTERS & ~CSRWriteM) // read-only + CSRCReadValM = HPMCOUNTER_REGW[CounterNumM]; + else begin + CSRCReadValM = '0; + IllegalCSRCAccessM = 1'b1; // requested CSR doesn't exist + end + end else begin // 32-bit counter reads + // Veril ator doesn't realize this only occurs for XLEN=32 + /* verilator lint_off WIDTH */ + if (CSRAdrM == TIME & ~CSRWriteM) CSRCReadValM = MTIME_CLINT[31:0];// TIME register is a shadow of the memory-mapped MTIME from the CLINT + else if (CSRAdrM == TIMEH & ~CSRWriteM) CSRCReadValM = MTIME_CLINT[63:32]; + /* verilator lint_on WIDTH */ + else if (CSRAdrM >= MHPMCOUNTERBASE & CSRAdrM < MHPMCOUNTERBASE+P.COUNTERS & CSRAdrM != MTIME) + CSRCReadValM = HPMCOUNTER_REGW[CounterNumM]; + else if (CSRAdrM >= HPMCOUNTERBASE & CSRAdrM < HPMCOUNTERBASE+P.COUNTERS & ~CSRWriteM) // read-only + CSRCReadValM = HPMCOUNTER_REGW[CounterNumM]; + else if (CSRAdrM >= MHPMCOUNTERHBASE & CSRAdrM < MHPMCOUNTERHBASE+P.COUNTERS & CSRAdrM != MTIMEH) + CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM]; + else if (CSRAdrM >= HPMCOUNTERHBASE & CSRAdrM < HPMCOUNTERHBASE+P.COUNTERS & ~CSRWriteM) // read-only + CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM]; + else begin CSRCReadValM = '0; - IllegalCSRCAccessM = 1'b1; // requested CSR doesn't exist + IllegalCSRCAccessM = 1'b1; // requested CSR doesn't exist + end end - end else begin // 32-bit counter reads - // Veril ator doesn't realize this only occurs for XLEN=32 - /* verilator lint_off WIDTH */ - if (CSRAdrM == TIME & ~CSRWriteM) CSRCReadValM = MTIME_CLINT[31:0];// TIME register is a shadow of the memory-mapped MTIME from the CLINT - else if (CSRAdrM == TIMEH & ~CSRWriteM) CSRCReadValM = MTIME_CLINT[63:32]; - /* verilator lint_on WIDTH */ - else if (CSRAdrM >= MHPMCOUNTERBASE & CSRAdrM < MHPMCOUNTERBASE+P.COUNTERS & CSRAdrM != MTIME) - CSRCReadValM = HPMCOUNTER_REGW[CounterNumM]; - else if (CSRAdrM >= HPMCOUNTERBASE & CSRAdrM < HPMCOUNTERBASE+P.COUNTERS & ~CSRWriteM) // read-only - CSRCReadValM = HPMCOUNTER_REGW[CounterNumM]; - else if (CSRAdrM >= MHPMCOUNTERHBASE & CSRAdrM < MHPMCOUNTERHBASE+P.COUNTERS & CSRAdrM != MTIMEH) - CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM]; - else if (CSRAdrM >= HPMCOUNTERHBASE & CSRAdrM < HPMCOUNTERHBASE+P.COUNTERS & ~CSRWriteM) // read-only - CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM]; - else begin - CSRCReadValM = '0; - IllegalCSRCAccessM = 1'b1; // requested CSR doesn't exist - end end end else begin CSRCReadValM = '0; From 69898f65da527ece235c4135cb8df2cd41b3d3c4 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 15 Oct 2024 09:09:42 -0700 Subject: [PATCH 4/9] Disabled some features in imperasdv not implemented by Wally --- config/rv32gc/imperas.ic | 18 ++++++++++++++++++ config/rv64gc/imperas.ic | 20 ++++++++++++++------ 2 files changed, 32 insertions(+), 6 deletions(-) diff --git a/config/rv32gc/imperas.ic b/config/rv32gc/imperas.ic index fe4a3dbed..9e9eef55f 100644 --- a/config/rv32gc/imperas.ic +++ b/config/rv32gc/imperas.ic @@ -59,6 +59,24 @@ #--override cpu/instret_undefined=T #--override cpu/hpmcounter_undefined=T +# context registers not implemented +--override cpu/scontext_undefined=T +--override cpu/mcontext_undefined=T + +# nonratified mnosie register not implemented +--override cpu/mnoise_undefined=T + +# mcause and scause only have 4 lsbs of code and 1 msb of interrupt flag +#--override cpu/ecode_mask=0x8000000F # for RV32 +--override cpu/ecode_mask=0x800000000000000F # for RV64 + +# Debug mode not yet supported +--override cpu/debug_mode=none + +# Zkr entropy source and seed register not supported. +--override cpu/Zkr=F + + --override cpu/reset_address=0x80000000 --override cpu/unaligned=F # Zicclsm (should be true) diff --git a/config/rv64gc/imperas.ic b/config/rv64gc/imperas.ic index 1b038c920..31584d22d 100644 --- a/config/rv64gc/imperas.ic +++ b/config/rv64gc/imperas.ic @@ -57,15 +57,23 @@ #--override cpu/instret_undefined=T #--override cpu/hpmcounter_undefined=T +# context registers not implemented --override cpu/scontext_undefined=T --override cpu/mcontext_undefined=T + +# nonratified mnosie register not implemented --override cpu/mnoise_undefined=T -# *** how to override other undefined registers: seed, mphmevent, mseccfg, debugger registers -#--override cpu/seed_undefined=T -#--override mhpmevent3_undefined=T -#--override cpu/mseccfg_undefined=T -#--override cpu/tselect_undefined=T -#--override cpu/tdata1_undefined=T + +# mcause and scause only have 4 lsbs of code and 1 msb of interrupt flag +#--override cpu/ecode_mask=0x8000000F # for RV32 +--override cpu/ecode_mask=0x800000000000000F # for RV64 + +# Debug mode not yet supported +--override cpu/debug_mode=none + +# Zkr entropy source and seed register not supported. +--override cpu/Zkr=F + --override cpu/reset_address=0x80000000 From 01805d9fb11784dfc9af437145f1fdc43df92eee Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 16 Oct 2024 13:26:20 -0700 Subject: [PATCH 5/9] Corrected RV32gc imperas configuration --- config/rv32gc/imperas.ic | 5 ----- 1 file changed, 5 deletions(-) diff --git a/config/rv32gc/imperas.ic b/config/rv32gc/imperas.ic index 9e9eef55f..eb4039216 100644 --- a/config/rv32gc/imperas.ic +++ b/config/rv32gc/imperas.ic @@ -63,9 +63,6 @@ --override cpu/scontext_undefined=T --override cpu/mcontext_undefined=T -# nonratified mnosie register not implemented ---override cpu/mnoise_undefined=T - # mcause and scause only have 4 lsbs of code and 1 msb of interrupt flag #--override cpu/ecode_mask=0x8000000F # for RV32 --override cpu/ecode_mask=0x800000000000000F # for RV64 @@ -73,8 +70,6 @@ # Debug mode not yet supported --override cpu/debug_mode=none -# Zkr entropy source and seed register not supported. ---override cpu/Zkr=F --override cpu/reset_address=0x80000000 From d21e2fa99711d2d4e72765226bc298f5f54fa5e4 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 16 Oct 2024 21:41:14 -0700 Subject: [PATCH 6/9] Increased timeout on regression-wally to avoid floating-point fcov runs from failing --- bin/regression-wally | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/regression-wally b/bin/regression-wally index 67cd4815b..1c9e09bfe 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -515,7 +515,7 @@ def main(): TIMEOUT_DUR = 20*60 os.system('rm -f questa/fcovrvvi_ucdb/* questa/fcovrvvi_logs/* questa/fcovrvvi/*') elif args.fcov: - TIMEOUT_DUR = 2*60 + TIMEOUT_DUR = 4*60 os.system('rm -f questa/fcov_ucdb/* questa/fcov_logs/* questa/fcov/*') elif args.buildroot: TIMEOUT_DUR = 60*1440 # 1 day From 9dcc0435b8a77fa95311424e790d400faa984605 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 16 Oct 2024 21:47:04 -0700 Subject: [PATCH 7/9] Increased timeout on regression-wally to avoid floating-point fcov runs from failing --- bin/regression-wally | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/regression-wally b/bin/regression-wally index 1c9e09bfe..a76836eea 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -515,7 +515,7 @@ def main(): TIMEOUT_DUR = 20*60 os.system('rm -f questa/fcovrvvi_ucdb/* questa/fcovrvvi_logs/* questa/fcovrvvi/*') elif args.fcov: - TIMEOUT_DUR = 4*60 + TIMEOUT_DUR = 8*60 os.system('rm -f questa/fcov_ucdb/* questa/fcov_logs/* questa/fcov/*') elif args.buildroot: TIMEOUT_DUR = 60*1440 # 1 day From 69cc36795bbe724021372c079aca68b1bc740a9f Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 22 Oct 2024 04:45:40 -0700 Subject: [PATCH 8/9] privileged coverage updates --- config/rv64gc/coverage.svh | 3 ++- sim/questa/wally.do | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh index d1bbaedbb..1629fb9da 100644 --- a/config/rv64gc/coverage.svh +++ b/config/rv64gc/coverage.svh @@ -9,7 +9,8 @@ `include "RV64M_coverage.svh" `include "RV64F_coverage.svh" `include "RV64Zfh_coverage.svh" -// `include "RV64VM_coverage.svh" +`include "RV64VM_coverage.svh" +`include "ZicsrM_coverage.svh" // `include "RV64VM_PMP_coverage.svh" // `include "RV64CBO_VM_coverage.svh" // `include "RV64CBO_PMP_coverage.svh" diff --git a/sim/questa/wally.do b/sim/questa/wally.do index d147080f3..f59e123f6 100644 --- a/sim/questa/wally.do +++ b/sim/questa/wally.do @@ -192,7 +192,7 @@ if {$DEBUG > 0} { # suppress spurious warnngs about # "Extra checking for conflicts with always_comb done at vopt time" # because vsim will run vopt -set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared +incdir+${FCRVVI} +incdir+${FCRVVI}/rv32 +incdir+${FCRVVI}/rv64 +incdir+${FCRVVI}/rv64_priv +incdir+${FCRVVI}/common +incdir+${FCRVVI}" +set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared +incdir+${FCRVVI} +incdir+${FCRVVI}/rv32 +incdir+${FCRVVI}/rv64 +incdir+${FCRVVI}/rv64_priv +incdir+${FCRVVI}/priv +incdir+${FCRVVI}/common +incdir+${FCRVVI}" set SOURCES "${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv" vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}${FCvlog} {*}${FCdefineCOVER_EXTS} {*}${lockstepvlog} ${FCdefineRVVI_COVERAGE} {*}${SOURCES} -suppress 2282,2583,7053,7063,2596,13286 From b848a1abfe22f6d3a4ec114acad68d0f0c32064b Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 22 Oct 2024 05:26:29 -0700 Subject: [PATCH 9/9] added no_pseudo_inst to only print regular instructions. --- config/rv32gc/imperas.ic | 2 ++ config/rv64gc/imperas.ic | 1 + 2 files changed, 3 insertions(+) diff --git a/config/rv32gc/imperas.ic b/config/rv32gc/imperas.ic index eb4039216..57c58c3e8 100644 --- a/config/rv32gc/imperas.ic +++ b/config/rv32gc/imperas.ic @@ -62,6 +62,8 @@ # context registers not implemented --override cpu/scontext_undefined=T --override cpu/mcontext_undefined=T +--override no_pseudo_inst=T # For code coverage, don't produce pseudoinstructions + # mcause and scause only have 4 lsbs of code and 1 msb of interrupt flag #--override cpu/ecode_mask=0x8000000F # for RV32 diff --git a/config/rv64gc/imperas.ic b/config/rv64gc/imperas.ic index 31584d22d..558fb8cae 100644 --- a/config/rv64gc/imperas.ic +++ b/config/rv64gc/imperas.ic @@ -60,6 +60,7 @@ # context registers not implemented --override cpu/scontext_undefined=T --override cpu/mcontext_undefined=T +--override no_pseudo_inst=T # For code coverage, don't produce pseudoinstructions # nonratified mnosie register not implemented --override cpu/mnoise_undefined=T