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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Renamed Flush to FlushStage in the cache.
This commit is contained in:
parent
284b97aff6
commit
b53f8eceef
8
pipelined/src/cache/cache.sv
vendored
8
pipelined/src/cache/cache.sv
vendored
@ -34,7 +34,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
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input logic clk,
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input logic clk,
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input logic reset,
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input logic reset,
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// cpu side
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// cpu side
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input logic Flush,
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input logic FlushStage,
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input logic CPUBusy,
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input logic CPUBusy,
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input logic [1:0] CacheRW,
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input logic [1:0] CacheRW,
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input logic [1:0] CacheAtomic,
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input logic [1:0] CacheAtomic,
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@ -126,11 +126,11 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
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cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN)
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cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN)
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CacheWays[NUMWAYS-1:0](.clk, .reset, .ce(SRAMEnable), .RAdr, .PAdr, .LineWriteData, .LineByteMask,
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CacheWays[NUMWAYS-1:0](.clk, .reset, .ce(SRAMEnable), .RAdr, .PAdr, .LineWriteData, .LineByteMask,
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.SetValidWay, .ClearValidWay, .SetDirtyWay, .ClearDirtyWay, .SelEvict, .VictimWay,
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.SetValidWay, .ClearValidWay, .SetDirtyWay, .ClearDirtyWay, .SelEvict, .VictimWay,
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.FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .VictimDirtyWay, .VictimTagWay, .Flush,
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.FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .VictimDirtyWay, .VictimTagWay, .FlushStage,
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.Invalidate(InvalidateCache));
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.Invalidate(InvalidateCache));
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if(NUMWAYS > 1) begin:vict
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if(NUMWAYS > 1) begin:vict
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cachereplacementpolicy #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cachereplacementpolicy(
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cachereplacementpolicy #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cachereplacementpolicy(
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.clk, .reset, .ce(SRAMEnable), .HitWay, .VictimWay, .RAdr, .LRUWriteEn(LRUWriteEn & ~Flush));
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.clk, .reset, .ce(SRAMEnable), .HitWay, .VictimWay, .RAdr, .LRUWriteEn(LRUWriteEn & ~FlushStage));
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end else assign VictimWay = 1'b1; // one hot.
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end else assign VictimWay = 1'b1; // one hot.
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assign CacheHit = | HitWay;
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assign CacheHit = | HitWay;
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assign VictimDirty = | VictimDirtyWay;
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assign VictimDirty = | VictimDirtyWay;
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@ -207,7 +207,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
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// Cache FSM
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// Cache FSM
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/////////////////////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////////////////////
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cachefsm cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck,
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cachefsm cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck,
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.Flush, .CacheRW, .CacheAtomic, .CPUBusy,
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.FlushStage, .CacheRW, .CacheAtomic, .CPUBusy,
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.CacheHit, .VictimDirty, .CacheStall, .CacheCommitted,
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.CacheHit, .VictimDirty, .CacheStall, .CacheCommitted,
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.CacheMiss, .CacheAccess, .SelAdr,
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.CacheMiss, .CacheAccess, .SelAdr,
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.ClearValid, .ClearDirty, .SetDirty,
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.ClearValid, .ClearDirty, .SetDirty,
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4
pipelined/src/cache/cachefsm.sv
vendored
4
pipelined/src/cache/cachefsm.sv
vendored
@ -34,7 +34,7 @@ module cachefsm
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(input logic clk,
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(input logic clk,
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input logic reset,
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input logic reset,
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// inputs from IEU
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// inputs from IEU
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input logic Flush,
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input logic FlushStage,
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input logic [1:0] CacheRW,
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input logic [1:0] CacheRW,
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input logic [1:0] CacheAtomic,
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input logic [1:0] CacheAtomic,
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input logic FlushCache,
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input logic FlushCache,
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@ -111,7 +111,7 @@ module cachefsm
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flop #(1) resetDelayReg(.clk, .d(reset), .q(resetDelay));
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flop #(1) resetDelayReg(.clk, .d(reset), .q(resetDelay));
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always_ff @(posedge clk)
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always_ff @(posedge clk)
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if (reset | Flush) CurrState <= #1 STATE_READY;
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if (reset | FlushStage) CurrState <= #1 STATE_READY;
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else CurrState <= #1 NextState;
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else CurrState <= #1 NextState;
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always_comb begin
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always_comb begin
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14
pipelined/src/cache/cacheway.sv
vendored
14
pipelined/src/cache/cacheway.sv
vendored
@ -48,7 +48,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
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input logic VictimWay,
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input logic VictimWay,
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input logic FlushWay,
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input logic FlushWay,
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input logic Invalidate,
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input logic Invalidate,
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input logic Flush,
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input logic FlushStage,
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// input logic [(`XLEN-1)/8:0] ByteMask,
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// input logic [(`XLEN-1)/8:0] ByteMask,
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input logic [LINELEN/8-1:0] LineByteMask,
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input logic [LINELEN/8-1:0] LineByteMask,
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@ -87,7 +87,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
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sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, .ce,
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sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, .ce,
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.addr(RAdr), .dout(ReadTag), .bwe('1),
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.addr(RAdr), .dout(ReadTag), .bwe('1),
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.din(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(SetValidWay & ~Flush));
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.din(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(SetValidWay & ~FlushStage));
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// AND portion of distributed tag multiplexer
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// AND portion of distributed tag multiplexer
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mux2 #(1) seltagmux(VictimWay, FlushWay, SelFlush, SelTag);
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mux2 #(1) seltagmux(VictimWay, FlushWay, SelFlush, SelTag);
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@ -110,7 +110,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
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sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce, .addr(RAdr),
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sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce, .addr(RAdr),
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.dout(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]),
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.dout(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]),
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.din(LineWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]),
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.din(LineWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]),
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.we(SelectedWriteWordEn & ~Flush), .bwe(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words]));
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.we(SelectedWriteWordEn & ~FlushStage), .bwe(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words]));
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end
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end
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// AND portion of distributed read multiplexers
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// AND portion of distributed read multiplexers
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@ -124,8 +124,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
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always_ff @(posedge clk) begin // Valid bit array,
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always_ff @(posedge clk) begin // Valid bit array,
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if (reset | Invalidate) ValidBits <= #1 '0;
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if (reset | Invalidate) ValidBits <= #1 '0;
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if(ce) begin Valid <= #1 ValidBits[RAdr];
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if(ce) begin Valid <= #1 ValidBits[RAdr];
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if (SetValidWay & ~Flush) ValidBits[RAdr] <= #1 1'b1;
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if (SetValidWay & ~FlushStage) ValidBits[RAdr] <= #1 1'b1;
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else if (ClearValidWay & ~Flush) ValidBits[RAdr] <= #1 1'b0;
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else if (ClearValidWay & ~FlushStage) ValidBits[RAdr] <= #1 1'b0;
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end
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end
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end
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end
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@ -139,8 +139,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
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if (reset) DirtyBits <= #1 {NUMLINES{1'b0}};
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if (reset) DirtyBits <= #1 {NUMLINES{1'b0}};
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if(ce) begin
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if(ce) begin
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Dirty <= #1 DirtyBits[RAdr];
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Dirty <= #1 DirtyBits[RAdr];
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if (SetDirtyWay & ~Flush) DirtyBits[RAdr] <= #1 1'b1;
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if (SetDirtyWay & ~FlushStage) DirtyBits[RAdr] <= #1 1'b1;
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else if (ClearDirtyWay & ~Flush) DirtyBits[RAdr] <= #1 1'b0;
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else if (ClearDirtyWay & ~FlushStage) DirtyBits[RAdr] <= #1 1'b0;
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end
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end
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end
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end
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end else assign Dirty = 1'b0;
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end else assign Dirty = 1'b0;
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@ -221,7 +221,7 @@ module ifu (
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cache #(.LINELEN(`ICACHE_LINELENINBITS),
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cache #(.LINELEN(`ICACHE_LINELENINBITS),
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.NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
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.NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
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.NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0))
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.NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0))
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icache(.clk, .reset, .Flush(FlushW), .CPUBusy,
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icache(.clk, .reset, .FlushStage(FlushW), .CPUBusy,
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.FetchBuffer, .CacheBusAck(ICacheBusAck),
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.FetchBuffer, .CacheBusAck(ICacheBusAck),
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.CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF),
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.CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF),
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.CacheBusRW,
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.CacheBusRW,
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@ -248,7 +248,7 @@ module lsu (
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cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
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cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
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.NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`LLEN), .DCACHE(1)) dcache(
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.NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`LLEN), .DCACHE(1)) dcache(
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.clk, .reset, .CPUBusy, .SelBusBeat, .Flush(FlushW), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM),
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.clk, .reset, .CPUBusy, .SelBusBeat, .FlushStage(FlushW), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM),
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.FlushCache(CacheFlushM), .NextAdr(IEUAdrE[11:0]), .PAdr(PAdrM),
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.FlushCache(CacheFlushM), .NextAdr(IEUAdrE[11:0]), .PAdr(PAdrM),
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.ByteMask(ByteMaskM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]),
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.ByteMask(ByteMaskM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]),
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.CacheWriteData(LSUWriteDataM), .SelHPTW,
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.CacheWriteData(LSUWriteDataM), .SelHPTW,
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