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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

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This commit is contained in:
Kip Macsai-Goren 2022-01-05 18:38:29 +00:00
commit b53ab27b26
84 changed files with 2747 additions and 3945 deletions
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17
bin/elf2hex.sh Executable file
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@ -0,0 +1,17 @@
#!/bin/sh
# james.stine@okstate.edu 4 Jan 2022
# Script to run elf2hex for memfile for
# Imperas and riscv-arch-test benchmarks
for file in work/rv64i_m/*/*.elf ; do
memfile=${file%.elf}.elf.memfile
echo riscv64-unknown-elf-elf2hex --bit-width 64 --input "$file" --output "$memfile"
riscv64-unknown-elf-elf2hex --bit-width 64 --input "$file" --output "$memfile"
done
for file in work/rv32i_m/*/*.elf ; do
memfile=${file%.elf}.elf.memfile
echo riscv64-unknown-elf-elf2hex --bit-width 32 --input "$file" --output "$memfile"
riscv64-unknown-elf-elf2hex --bit-width 32 --input "$file" --output "$memfile"
done

6
pipelined/config/buildroot/wally-config.vh
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@ -62,14 +62,14 @@
`define DTLB_ENTRIES 32 `define DTLB_ENTRIES 32
// Cache configuration. Sizes should be a power of two // Cache configuration. Sizes should be a power of two
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks // typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
`define DCACHE_NUMWAYS 4 `define DCACHE_NUMWAYS 4
`define DCACHE_WAYSIZEINBYTES 4096 `define DCACHE_WAYSIZEINBYTES 4096
`define DCACHE_BLOCKLENINBITS 256 `define DCACHE_LINELENINBITS 256
`define DCACHE_REPLBITS 3 `define DCACHE_REPLBITS 3
`define ICACHE_NUMWAYS 4 `define ICACHE_NUMWAYS 4
`define ICACHE_WAYSIZEINBYTES 4096 `define ICACHE_WAYSIZEINBYTES 4096
`define ICACHE_BLOCKLENINBITS 256 `define ICACHE_LINELENINBITS 256
// Integer Divider Configuration // Integer Divider Configuration
// DIV_BITSPERCYCLE must be 1, 2, or 4 // DIV_BITSPERCYCLE must be 1, 2, or 4

6
pipelined/config/busybear/wally-config.vh
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@ -60,14 +60,14 @@
`define DTLB_ENTRIES 32 `define DTLB_ENTRIES 32
// Cache configuration. Sizes should be a power of two // Cache configuration. Sizes should be a power of two
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks // typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
`define DCACHE_NUMWAYS 4 `define DCACHE_NUMWAYS 4
`define DCACHE_WAYSIZEINBYTES 2048 `define DCACHE_WAYSIZEINBYTES 2048
`define DCACHE_BLOCKLENINBITS 256 `define DCACHE_LINELENINBITS 256
`define DCACHE_REPLBITS 3 `define DCACHE_REPLBITS 3
`define ICACHE_NUMWAYS 1 `define ICACHE_NUMWAYS 1
`define ICACHE_WAYSIZEINBYTES 4096 `define ICACHE_WAYSIZEINBYTES 4096
`define ICACHE_BLOCKLENINBITS 256 `define ICACHE_LINELENINBITS 256
// Integer Divider Configuration // Integer Divider Configuration
// DIV_BITSPERCYCLE must be 1, 2, or 4 // DIV_BITSPERCYCLE must be 1, 2, or 4

6
pipelined/config/coremark/wally-config.vh
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@ -62,14 +62,14 @@
`define DTLB_ENTRIES 32 `define DTLB_ENTRIES 32
// Cache configuration. Sizes should be a power of two // Cache configuration. Sizes should be a power of two
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks // typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
`define DCACHE_NUMWAYS 4 `define DCACHE_NUMWAYS 4
`define DCACHE_WAYSIZEINBYTES 2048 `define DCACHE_WAYSIZEINBYTES 2048
`define DCACHE_BLOCKLENINBITS 256 `define DCACHE_LINELENINBITS 256
`define DCACHE_REPLBITS 3 `define DCACHE_REPLBITS 3
`define ICACHE_NUMWAYS 1 `define ICACHE_NUMWAYS 1
`define ICACHE_WAYSIZEINBYTES 4096 `define ICACHE_WAYSIZEINBYTES 4096
`define ICACHE_BLOCKLENINBITS 256 `define ICACHE_LINELENINBITS 256
// Integer Divider Configuration // Integer Divider Configuration
// DIV_BITSPERCYCLE must be 1, 2, or 4 // DIV_BITSPERCYCLE must be 1, 2, or 4

6
pipelined/config/coremark_bare/wally-config.vh
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@ -63,13 +63,13 @@
`define DTLB_ENTRIES 32 `define DTLB_ENTRIES 32
// Cache configuration. Sizes should be a power of two // Cache configuration. Sizes should be a power of two
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks // typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
`define DCACHE_NUMWAYS 4 `define DCACHE_NUMWAYS 4
`define DCACHE_WAYSIZEINBYTES 4096 `define DCACHE_WAYSIZEINBYTES 4096
`define DCACHE_BLOCKLENINBITS 256 `define DCACHE_LINELENINBITS 256
`define ICACHE_NUMWAYS 4 `define ICACHE_NUMWAYS 4
`define ICACHE_WAYSIZEINBYTES 4096 `define ICACHE_WAYSIZEINBYTES 4096
`define ICACHE_BLOCKLENINBITS 256 `define ICACHE_LINELENINBITS 256
// Integer Divider Configuration // Integer Divider Configuration
// DIV_BITSPERCYCLE must be 1, 2, or 4 // DIV_BITSPERCYCLE must be 1, 2, or 4

6
pipelined/config/fpga/wally-config.vh
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@ -62,14 +62,14 @@
`define DTLB_ENTRIES 32 `define DTLB_ENTRIES 32
// Cache configuration. Sizes should be a power of two // Cache configuration. Sizes should be a power of two
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks // typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
`define DCACHE_NUMWAYS 4 `define DCACHE_NUMWAYS 4
`define DCACHE_WAYSIZEINBYTES 4096 `define DCACHE_WAYSIZEINBYTES 4096
`define DCACHE_BLOCKLENINBITS 256 `define DCACHE_LINELENINBITS 256
`define DCACHE_REPLBITS 3 `define DCACHE_REPLBITS 3
`define ICACHE_NUMWAYS 4 `define ICACHE_NUMWAYS 4
`define ICACHE_WAYSIZEINBYTES 4096 `define ICACHE_WAYSIZEINBYTES 4096
`define ICACHE_BLOCKLENINBITS 256 `define ICACHE_LINELENINBITS 256
// Integer Divider Configuration // Integer Divider Configuration
// DIV_BITSPERCYCLE must be 1, 2, or 4 // DIV_BITSPERCYCLE must be 1, 2, or 4

6
pipelined/config/rv32gc/wally-config.vh
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@ -61,14 +61,14 @@
`define DTLB_ENTRIES 32 `define DTLB_ENTRIES 32
// Cache configuration. Sizes should be a power of two // Cache configuration. Sizes should be a power of two
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks // typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
`define DCACHE_NUMWAYS 4 `define DCACHE_NUMWAYS 4
`define DCACHE_WAYSIZEINBYTES 4096 `define DCACHE_WAYSIZEINBYTES 4096
`define DCACHE_BLOCKLENINBITS 256 `define DCACHE_LINELENINBITS 256
`define DCACHE_REPLBITS 3 `define DCACHE_REPLBITS 3
`define ICACHE_NUMWAYS 4 `define ICACHE_NUMWAYS 4
`define ICACHE_WAYSIZEINBYTES 4096 `define ICACHE_WAYSIZEINBYTES 4096
`define ICACHE_BLOCKLENINBITS 256 `define ICACHE_LINELENINBITS 256
// Integer Divider Configuration // Integer Divider Configuration
// DIV_BITSPERCYCLE must be 1, 2, or 4 // DIV_BITSPERCYCLE must be 1, 2, or 4

6
pipelined/config/rv32ic/wally-config.vh
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@ -61,14 +61,14 @@
`define DTLB_ENTRIES 0 `define DTLB_ENTRIES 0
// Cache configuration. Sizes should be a power of two // Cache configuration. Sizes should be a power of two
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks // typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
`define DCACHE_NUMWAYS 4 `define DCACHE_NUMWAYS 4
`define DCACHE_WAYSIZEINBYTES 4096 `define DCACHE_WAYSIZEINBYTES 4096
`define DCACHE_BLOCKLENINBITS 256 `define DCACHE_LINELENINBITS 256
`define DCACHE_REPLBITS 3 `define DCACHE_REPLBITS 3
`define ICACHE_NUMWAYS 4 `define ICACHE_NUMWAYS 4
`define ICACHE_WAYSIZEINBYTES 4096 `define ICACHE_WAYSIZEINBYTES 4096
`define ICACHE_BLOCKLENINBITS 256 `define ICACHE_LINELENINBITS 256
// Integer Divider Configuration // Integer Divider Configuration
// DIV_BITSPERCYCLE must be 1, 2, or 4 // DIV_BITSPERCYCLE must be 1, 2, or 4

6
pipelined/config/rv64BP/wally-config.vh
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@ -63,14 +63,14 @@
`define DTLB_ENTRIES 32 `define DTLB_ENTRIES 32
// Cache configuration. Sizes should be a power of two // Cache configuration. Sizes should be a power of two
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks // typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
`define DCACHE_NUMWAYS 4 `define DCACHE_NUMWAYS 4
`define DCACHE_WAYSIZEINBYTES 4096 `define DCACHE_WAYSIZEINBYTES 4096
`define DCACHE_BLOCKLENINBITS 256 `define DCACHE_LINELENINBITS 256
`define DCACHE_REPLBITS 3 `define DCACHE_REPLBITS 3
`define ICACHE_NUMWAYS 4 `define ICACHE_NUMWAYS 4
`define ICACHE_WAYSIZEINBYTES 4096 `define ICACHE_WAYSIZEINBYTES 4096
`define ICACHE_BLOCKLENINBITS 256 `define ICACHE_LINELENINBITS 256
// Legal number of PMP entries are 0, 16, or 64 // Legal number of PMP entries are 0, 16, or 64
`define PMP_ENTRIES 64 `define PMP_ENTRIES 64

6
pipelined/config/rv64gc/wally-config.vh
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@ -62,14 +62,14 @@
`define DTLB_ENTRIES 32 `define DTLB_ENTRIES 32
// Cache configuration. Sizes should be a power of two // Cache configuration. Sizes should be a power of two
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks // typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
`define DCACHE_NUMWAYS 4 `define DCACHE_NUMWAYS 4
`define DCACHE_WAYSIZEINBYTES 4096 `define DCACHE_WAYSIZEINBYTES 4096
`define DCACHE_BLOCKLENINBITS 256 `define DCACHE_LINELENINBITS 256
`define DCACHE_REPLBITS 3 `define DCACHE_REPLBITS 3
`define ICACHE_NUMWAYS 4 `define ICACHE_NUMWAYS 4
`define ICACHE_WAYSIZEINBYTES 4096 `define ICACHE_WAYSIZEINBYTES 4096
`define ICACHE_BLOCKLENINBITS 256 `define ICACHE_LINELENINBITS 256
// Integer Divider Configuration // Integer Divider Configuration
// DIV_BITSPERCYCLE must be 1, 2, or 4 // DIV_BITSPERCYCLE must be 1, 2, or 4

6
pipelined/config/rv64ic/wally-config.vh
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@ -62,14 +62,14 @@
`define DTLB_ENTRIES 32 `define DTLB_ENTRIES 32
// Cache configuration. Sizes should be a power of two // Cache configuration. Sizes should be a power of two
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks // typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
`define DCACHE_NUMWAYS 4 `define DCACHE_NUMWAYS 4
`define DCACHE_WAYSIZEINBYTES 4096 `define DCACHE_WAYSIZEINBYTES 4096
`define DCACHE_BLOCKLENINBITS 256 `define DCACHE_LINELENINBITS 256
`define DCACHE_REPLBITS 3 `define DCACHE_REPLBITS 3
`define ICACHE_NUMWAYS 4 `define ICACHE_NUMWAYS 4
`define ICACHE_WAYSIZEINBYTES 4096 `define ICACHE_WAYSIZEINBYTES 4096
`define ICACHE_BLOCKLENINBITS 256 `define ICACHE_LINELENINBITS 256
// Integer Divider Configuration // Integer Divider Configuration
// DIV_BITSPERCYCLE must be 1, 2, or 4 // DIV_BITSPERCYCLE must be 1, 2, or 4

2
pipelined/fpu-testfloat/FMA/tbgen/tb.sv
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@ -153,7 +153,7 @@ fma2 UUT2(.XSgnM(XSgnE), .YSgnM(YSgnE), .XExpM(XExpE), .YExpM(YExpE), .ZExpM(ZEx
.FmtM(FmtE), .FrmM(FrmE), .FMAFlgM, .FMAResM); .FmtM(FmtE), .FrmM(FrmE), .FMAFlgM, .FMAResM);
// generate clock // produce clock
always always
begin begin
clk = 1; #5; clk = 0; #5; clk = 1; #5; clk = 0; #5;

2
pipelined/ppa/ppa.sv
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@ -45,14 +45,12 @@ endmodule
module INVX2(input logic a, output logic y); module INVX2(input logic a, output logic y);
generate
if (LIB == SKY130) if (LIB == SKY130)
sky130_osu_sc_12T_ms__inv_2 inv(a, y); sky130_osu_sc_12T_ms__inv_2 inv(a, y);
else if (LIB == SKL90) else if (LIB == SKL90)
scc9gena_inv_2 inv(a, y) scc9gena_inv_2 inv(a, y)
else if (LIB == GF14) else if (LIB == GF14)
INV_X2N_A10P5PP84TSL_C14(a, y) INV_X2N_A10P5PP84TSL_C14(a, y)
endgenerate
endmodule endmodule
module driver #(parameter WDITH=1) ( module driver #(parameter WDITH=1) (

5
pipelined/regression/Makefile
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@ -3,11 +3,16 @@ make all:
make -C ../../addins/riscv-arch-test make -C ../../addins/riscv-arch-test
make -C ../../addins/riscv-arch-test XLEN=32 make -C ../../addins/riscv-arch-test XLEN=32
exe2memfile.pl ../../addins/riscv-arch-test/work/*/*/*.elf exe2memfile.pl ../../addins/riscv-arch-test/work/*/*/*.elf
# extractFunctionRadix. ***
# Build wally-riscv-arch-test # Build wally-riscv-arch-test
make -C ../../tests/wally-riscv-arch-test/ make -C ../../tests/wally-riscv-arch-test/
make -C ../../tests/wally-riscv-arch-test/ XLEN=32 make -C ../../tests/wally-riscv-arch-test/ XLEN=32
exe2memfile.pl ../../tests/wally-riscv-arch-test/work/*/*/*.elf exe2memfile.pl ../../tests/wally-riscv-arch-test/work/*/*/*.elf
# ***extractFunctionRadix
# *** use elf2hex
# *** add optional imperas tests
# Link Linux test vectors (fix this later***) # Link Linux test vectors (fix this later***)
#cd ../../tests/linux-testgen/linux-testvectors/;./tvLinker.sh #cd ../../tests/linux-testgen/linux-testvectors/;./tvLinker.sh

4
pipelined/regression/regression-wally.py
View File

@ -51,7 +51,7 @@ tc = TestCase(
grepstr="400100000 instructions") grepstr="400100000 instructions")
configs.append(tc) configs.append(tc)
tests64gc = ["arch64i", "arch64priv", "arch64c", "arch64m", "arch64d", "imperas64i", "imperas64f", "imperas64d", "imperas64p", "imperas64m", "imperas64a", "imperas64c", "wally64priv", "imperas64mmu"] # "wally64i", #, "testsBP64"] tests64gc = ["arch64i", "arch64priv", "arch64c", "arch64m", "arch64d", "imperas64i", "imperas64f", "imperas64d", "imperas64p", "imperas64m", "imperas64a", "imperas64c", "wally64priv"] # , "imperas64mmu" "wally64i", #, "testsBP64"]
for test in tests64gc: for test in tests64gc:
tc = TestCase( tc = TestCase(
name=test, name=test,
@ -59,7 +59,7 @@ for test in tests64gc:
cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv64gc "+test+"\n!", cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv64gc "+test+"\n!",
grepstr="All tests ran without failures") grepstr="All tests ran without failures")
configs.append(tc) configs.append(tc)
tests32gc = ["arch32i", "arch32priv", "arch32c", "arch32m", "arch32f", "imperas32i", "imperas32f", "imperas32p", "imperas32m", "imperas32a", "imperas32c", "wally32priv", "imperas32mmu"] #"wally32i", tests32gc = ["arch32i", "arch32priv", "arch32c", "arch32m", "arch32f", "imperas32i", "imperas32f", "imperas32p", "imperas32m", "imperas32a", "imperas32c", "wally32priv"] #, "imperas32mmu""wally32i",
for test in tests32gc: for test in tests32gc:
tc = TestCase( tc = TestCase(
name=test, name=test,

2
pipelined/regression/sim-wally-batch
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@ -1,3 +1,3 @@
vsim -c <<! vsim -c <<!
do wally-pipelined-batch.do rv64gc imperas64i do wally-pipelined-batch.do rv32gc wally32priv
! !

404
pipelined/regression/wave.do
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@ -176,182 +176,183 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HMASTLOCK
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
add wave -noupdate -group lsu -color Gold /testbench/dut/hart/lsu/MEM_VIRTMEM/interlockfsm/InterlockCurrState add wave -noupdate -expand -group lsu -color Gold /testbench/dut/hart/lsu/MEM_VIRTMEM/interlockfsm/InterlockCurrState
add wave -noupdate -group lsu /testbench/dut/hart/lsu/SelHPTW add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/SelHPTW
add wave -noupdate -group lsu /testbench/dut/hart/lsu/InterlockStall add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/InterlockStall
add wave -noupdate -group lsu /testbench/dut/hart/lsu/LSUStall add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/LSUStall
add wave -noupdate -group lsu /testbench/dut/hart/lsu/ReadDataWordMuxM add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/ReadDataWordMuxM
add wave -noupdate -group lsu /testbench/dut/hart/lsu/ReadDataM add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/ReadDataM
add wave -noupdate -group lsu /testbench/dut/hart/lsu/WriteDataM add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WriteDataM
add wave -noupdate -group lsu /testbench/dut/hart/lsu/SelUncachedAdr add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/SelUncachedAdr
add wave -noupdate -group lsu -expand -group bus -color Gold /testbench/dut/hart/lsu/busfsm/BusCurrState add wave -noupdate -expand -group lsu -expand -group bus -color Gold /testbench/dut/hart/lsu/busfsm/BusCurrState
add wave -noupdate -group lsu -expand -group bus /testbench/dut/hart/lsu/BusStall add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/BusStall
add wave -noupdate -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusRead add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusRead
add wave -noupdate -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusWrite add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusWrite
add wave -noupdate -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusAdr add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusAdr
add wave -noupdate -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusAck add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusAck
add wave -noupdate -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusHWDATA add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusHWDATA
add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcache/dcachefsm/CurrState add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcache/dcachefsm/CurrState
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/WayHit add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/WayHit
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMBlockWriteEnableM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMBlockWriteEnableM
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWordWriteEnableM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWordWriteEnableM
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWayWriteEnable add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWayWriteEnable
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWordEnable add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWordEnable
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMBlockWayWriteEnableM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMBlockWayWriteEnableM
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SelAdrM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SelAdrM
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/MEM_VIRTMEM/SelReplayCPURequest add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/MEM_VIRTMEM/SelReplayCPURequest
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrE add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrE
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrM add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrM
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/RAdr add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/RAdr
add wave -noupdate -group lsu -expand -group dcache -group flush -radix unsigned /testbench/dut/hart/lsu/dcache/dcache/FlushAdr add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush -radix unsigned /testbench/dut/hart/lsu/dcache/dcache/FlushAdr
add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/dcache/FlushWay add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush -radix unsigned /testbench/dut/hart/lsu/dcache/dcache/FlushAdrQ
add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/dcache/VictimDirtyWay add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/hart/lsu/dcache/dcache/FlushWay
add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/dcache/VictimTag add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/hart/lsu/dcache/dcache/VictimDirtyWay
add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/dcache/CacheableM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/hart/lsu/dcache/dcache/VictimTag
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/DCacheMemWriteData add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/hart/lsu/dcache/dcache/CacheableM
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/WriteEnable} add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/DCacheMemWriteData
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/SetValid} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/SetDirty} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/SetValid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/CacheTagMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/SetDirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/DirtyBits} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/CacheTagMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/ValidBits} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/DirtyBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/ValidBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/DirtyBits} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/ValidBits} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/DirtyBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/SetDirty} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/ValidBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/WriteEnable} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/SetDirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/WriteWordEnable} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/CacheTagMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/WriteWordEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/CacheTagMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/WriteEnable} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/SetValid} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/SetDirty} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/SetValid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/CacheTagMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/SetDirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/DirtyBits} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/CacheTagMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/ValidBits} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/DirtyBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/ValidBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/WriteEnable} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/SetValid} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/SetDirty} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/SetValid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ClearDirty} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/SetDirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/VDWriteEnable} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ClearDirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/CacheTagMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/VDWriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/DirtyBits} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/CacheTagMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ValidBits} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/DirtyBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ValidBits}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData} add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/SetValid add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/ClearValid add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/SetValid
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/SetDirty add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/ClearValid
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/ClearDirty add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/SetDirty
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/RAdr add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/ClearDirty
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/WayHit} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/RAdr
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/Valid} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/WayHit}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/Dirty} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/Valid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/ReadTag} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/Dirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/WayHit} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/ReadTag}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/Valid} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/WayHit}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/Dirty} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/Valid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/ReadTag} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/Dirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/WayHit} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/ReadTag}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/Valid} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/WayHit}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/Dirty} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/Valid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/ReadTag} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/Dirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/WayHit} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/ReadTag}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/Valid} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/WayHit}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/Dirty} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/Valid}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ReadTag} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/Dirty}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/WayHit add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ReadTag}
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/ReadDataWordM add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/WayHit
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimTag add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/ReadDataWordM
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimWay add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimTag
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimDirtyWay add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimWay
add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimDirty add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimDirtyWay
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuRWM add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimDirty
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuAdrE add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuRWM
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuPAdrM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuAdrE
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuAtomicM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuPAdrM
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/CacheableM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuAtomicM
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/FlushDCacheM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/CacheableM
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/DCacheStall add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/FlushDCacheM
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/ReadDataWordM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/DCacheStall
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/FinalWriteDataM add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/ReadDataWordM
add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/dcache/WayHit add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/FinalWriteDataM
add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/dcache/CacheHit add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/dcache/WayHit
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheFetchLine add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/dcache/CacheHit
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheWriteLine add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheFetchLine
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheMemWriteData add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheWriteLine
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheBusAck add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheMemWriteData
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/FlushWay add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheBusAck
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/VAdr add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/FlushWay
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/VAdr
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/PTE add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/HitPageType add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/PTE
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/HitPageType
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/TLBMiss add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/TLBHit add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/TLBMiss
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/PhysicalAddress add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/TLBHit
add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/dmmu/TLBPageFault add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/PhysicalAddress
add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/dmmu/LoadAccessFaultM add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/dmmu/TLBPageFault
add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/dmmu/StoreAccessFaultM add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/dmmu/LoadAccessFaultM
add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/dmmu/StoreAccessFaultM
add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/PTE add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/PTE
add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/TLBWrite add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/pmachecker/PhysicalAddress add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/pmachecker/SelRegions add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/Cacheable add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/pmachecker/SelRegions
add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/Idempotent add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/Cacheable
add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/AtomicAllowed add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/Idempotent
add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/pmachecker/PMAAccessFault add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/AtomicAllowed
add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/PMAInstrAccessFaultF add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/PMALoadAccessFaultM add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/PMAInstrAccessFaultF
add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/PMAStoreAccessFaultM add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/PMALoadAccessFaultM
add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/PMAStoreAccessFaultM
add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/ReadAccessM add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress
add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/WriteAccessM add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/ReadAccessM
add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/WriteAccessM
add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW
add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/PMPInstrAccessFaultF add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW
add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/PMPLoadAccessFaultM add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/PMPInstrAccessFaultF
add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/PMPStoreAccessFaultM add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/PMPLoadAccessFaultM
add wave -noupdate -group lsu -group ptwalker -color Gold /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/WalkerState add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/PMPStoreAccessFaultM
add wave -noupdate -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/PCF add wave -noupdate -expand -group lsu -group ptwalker -color Gold /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/WalkerState
add wave -noupdate -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWReadPTE add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/PCF
add wave -noupdate -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWAdr add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWReadPTE
add wave -noupdate -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/PTE add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWAdr
add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/ITLBMissF add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/PTE
add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/DTLBMissM add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/ITLBMissF
add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/ITLBWriteF add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/DTLBMissM
add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/DTLBWriteM add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/ITLBWriteF
add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/DTLBWriteM
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HCLK add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HCLK
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HSELPLIC add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HSELPLIC
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HADDR add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HADDR
@ -432,37 +433,30 @@ add wave -noupdate /testbench/dut/hart/lsu/LocalLsuBusAdr
add wave -noupdate /testbench/dut/hart/lsu/busfsm/BusNextState add wave -noupdate /testbench/dut/hart/lsu/busfsm/BusNextState
add wave -noupdate /testbench/dut/hart/lsu/busfsm/DCacheFetchLine add wave -noupdate /testbench/dut/hart/lsu/busfsm/DCacheFetchLine
add wave -noupdate /testbench/dut/hart/lsu/busfsm/DCacheWriteLine add wave -noupdate /testbench/dut/hart/lsu/busfsm/DCacheWriteLine
add wave -noupdate -expand -group ifu -color Gold /testbench/dut/hart/ifu/busfsm/BusCurrState add wave -noupdate -group ifu -color Gold /testbench/dut/hart/ifu/busfsm/BusCurrState
add wave -noupdate -expand -group ifu /testbench/dut/hart/ifu/busfsm/LsuBusAck add wave -noupdate -group ifu /testbench/dut/hart/ifu/busfsm/LsuBusAck
add wave -noupdate -expand -group ifu -expand -group icache -color Gold /testbench/dut/hart/ifu/icache/icache/icachefsm/CurrState add wave -noupdate -group ifu -expand -group icache -color Gold /testbench/dut/hart/ifu/icache/icache/icachefsm/CurrState
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/icachefsm/NextState add wave -noupdate -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/icachefsm/NextState
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/ITLBMissF add wave -noupdate -group ifu -expand -group icache /testbench/dut/hart/ifu/ITLBMissF
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/ITLBWriteF add wave -noupdate -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/ReadLineF
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/ReadLineF add wave -noupdate -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/SelAdr
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/SelAdr add wave -noupdate -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/PCNextF
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/PCNextF add wave -noupdate -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/PCPF
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/PCPF add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/icachefsm/hit
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/PCPSpillF add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/icachefsm/ICacheStallF
add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/icachefsm/hit add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/icachefsm/PreCntEn
add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/icachefsm/spill add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/FinalInstrRawF
add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/icachefsm/ICacheStallF add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/icache/ICacheBusAdr
add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/icachefsm/spillSave add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/icache/icachefsm/ICacheBusAck
add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/icachefsm/spillSave add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/icache/icachefsm/ICacheMemWriteEnable
add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/icachefsm/PreCntEn add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/icache/ICacheMemWriteData
add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/FinalInstrRawF add wave -noupdate -group ifu -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/icache/ICacheBusAdr add wave -noupdate -group ifu -group itlb /testbench/dut/hart/ifu/ITLBMissF
add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/icache/icachefsm/ICacheBusAck add wave -noupdate -group ifu -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/icache/icachefsm/ICacheMemWriteEnable
add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/icache/ICacheMemWriteData
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/ICacheMemReadData
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/SpillDataBlock0
add wave -noupdate -expand -group ifu -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
add wave -noupdate -expand -group ifu -group itlb /testbench/dut/hart/ifu/ITLBMissF
add wave -noupdate -expand -group ifu -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
add wave -noupdate /testbench/dut/hart/ifu/IfuBusRead add wave -noupdate /testbench/dut/hart/ifu/IfuBusRead
add wave -noupdate /testbench/dut/hart/ifu/icache/icache/ICacheFetchLine add wave -noupdate /testbench/dut/hart/ifu/icache/icache/ICacheFetchLine
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 7} {36865 ns} 1} {{Cursor 5} {49445 ns} 1} {{Cursor 3} {1239086 ns} 0} {{Cursor 4} {49574 ns} 1} WaveRestoreCursors {{Cursor 7} {36865 ns} 1} {{Cursor 5} {49445 ns} 1} {{Cursor 3} {38453 ns} 0} {{Cursor 4} {49574 ns} 1}
quietly wave cursor active 3 quietly wave cursor active 3
configure wave -namecolwidth 250 configure wave -namecolwidth 250
configure wave -valuecolwidth 314 configure wave -valuecolwidth 314
@ -478,4 +472,4 @@ configure wave -griddelta 40
configure wave -timeline 0 configure wave -timeline 0
configure wave -timelineunits ns configure wave -timelineunits ns
update update
WaveRestoreZoom {1238897 ns} {1239273 ns} WaveRestoreZoom {38413 ns} {39039 ns}

269
pipelined/src/cache/cache.sv vendored Normal file
View File

@ -0,0 +1,269 @@
///////////////////////////////////////////
// cache (data cache)
//
// Written: ross1728@gmail.com July 07, 2021
// Implements the L1 data cache
//
// Purpose: Storage for data and meta data.
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-config.vh"
module cache #(parameter integer LINELEN,
parameter integer NUMLINES,
parameter integer NUMWAYS,
parameter integer DCACHE = 1)
(input logic clk,
input logic reset,
input logic CPUBusy,
// cpu side
input logic [1:0] RW,
input logic [1:0] Atomic,
input logic FlushCache,
input logic [11:0] LsuAdrE, // virtual address, but we only use the lower 12 bits.
input logic [`PA_BITS-1:0] LsuPAdrM, // physical address
input logic [11:0] PreLsuPAdrM, // physical or virtual address
input logic [`XLEN-1:0] FinalWriteData,
output logic [`XLEN-1:0] ReadDataWord,
output logic CacheCommitted,
// Bus fsm interface
input logic IgnoreRequest,
output logic CacheFetchLine,
output logic CacheWriteLine,
input logic CacheBusAck,
output logic [`PA_BITS-1:0] CacheBusAdr,
input logic [LINELEN-1:0] CacheMemWriteData,
output logic [`XLEN-1:0] ReadDataLineSets [(LINELEN/`XLEN)-1:0],
output logic CacheStall,
// to performance counters
output logic CacheMiss,
output logic CacheAccess,
input logic InvalidateCacheM
);
localparam integer LINEBYTELEN = LINELEN/8;
localparam integer OFFSETLEN = $clog2(LINEBYTELEN);
localparam integer INDEXLEN = $clog2(NUMLINES);
localparam integer TAGLEN = `PA_BITS - OFFSETLEN - INDEXLEN;
localparam integer WORDSPERLINE = LINELEN/`XLEN;
localparam integer LOGWPL = $clog2(WORDSPERLINE);
localparam integer LOGXLENBYTES = $clog2(`XLEN/8);
localparam integer FlushAdrThreshold = NUMLINES;
logic [1:0] SelAdrM;
logic [INDEXLEN-1:0] RAdr;
logic [LINELEN-1:0] SRAMWriteData;
logic SetValid, ClearValid;
logic SetDirty, ClearDirty;
logic [LINELEN-1:0] ReadDataLineWayMasked [NUMWAYS-1:0];
logic [NUMWAYS-1:0] WayHit;
logic CacheHit;
logic [LINELEN-1:0] ReadDataLineM;
logic [WORDSPERLINE-1:0] SRAMWordEnable;
logic SRAMWordWriteEnableM;
logic SRAMLineWriteEnableM;
logic [NUMWAYS-1:0] SRAMLineWayWriteEnableM;
logic [NUMWAYS-1:0] SRAMWayWriteEnable;
logic [NUMWAYS-1:0] VictimWay;
logic [NUMWAYS-1:0] VictimDirtyWay;
logic VictimDirty;
logic [2**LOGWPL-1:0] MemPAdrDecodedW;
logic [TAGLEN-1:0] VictimTagWay [NUMWAYS-1:0];
logic [TAGLEN-1:0] VictimTag;
logic [INDEXLEN-1:0] FlushAdr;
logic [INDEXLEN-1:0] FlushAdrP1;
logic [INDEXLEN-1:0] FlushAdrQ;
logic FlushAdrCntEn;
logic FlushAdrCntRst;
logic FlushAdrFlag;
logic [NUMWAYS-1:0] FlushWay;
logic [NUMWAYS-1:0] NextFlushWay;
logic FlushWayCntEn;
logic FlushWayCntRst;
logic VDWriteEnable;
logic SelEvict;
logic LRUWriteEn;
logic [NUMWAYS-1:0] VDWriteEnableWay;
logic SelFlush;
// Read Path CPU (IEU) side
mux3 #(INDEXLEN)
AdrSelMux(.d0(LsuAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
.d1(PreLsuPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
.d2(FlushAdr),
.s(SelAdrM),
.y(RAdr));
cacheway #(.NUMLINES(NUMLINES), .LINELEN(LINELEN), .TAGLEN(TAGLEN),
.OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN))
MemWay[NUMWAYS-1:0](.clk, .reset, .RAdr,
.PAdr(LsuPAdrM),
.WriteEnable(SRAMWayWriteEnable),
.VDWriteEnable(VDWriteEnableWay),
.WriteWordEnable(SRAMWordEnable),
.TagWriteEnable(SRAMLineWayWriteEnableM),
.WriteData(SRAMWriteData),
.SetValid, .ClearValid, .SetDirty, .ClearDirty, .SelEvict,
.VictimWay, .FlushWay, .SelFlush,
.ReadDataLineWayMasked,
.WayHit, .VictimDirtyWay, .VictimTagWay,
.InvalidateAll(InvalidateCacheM));
if(NUMWAYS > 1) begin:vict
cachereplacementpolicy #(NUMWAYS, INDEXLEN, OFFSETLEN, NUMLINES)
cachereplacementpolicy(.clk, .reset,
.WayHit,
.VictimWay,
.LsuPAdrM(LsuPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
.RAdr,
.LRUWriteEn);
end else begin:vict
assign VictimWay = 1'b1; // one hot.
end
assign CacheHit = | WayHit;
assign VictimDirty = | VictimDirtyWay;
// ReadDataLineWayMaskedM is a 2d array of cache line len by number of ways.
// Need to OR together each way in a bitwise manner.
// Final part of the AO Mux. First is the AND in the cacheway.
or_rows #(NUMWAYS, LINELEN) ReadDataAOMux(.a(ReadDataLineWayMasked), .y(ReadDataLineM));
or_rows #(NUMWAYS, TAGLEN) VictimTagAOMux(.a(VictimTagWay), .y(VictimTag));
// Convert the Read data bus ReadDataSelectWay into sets of XLEN so we can
// easily build a variable input mux.
// *** consider using a limited range shift to do this final muxing.
genvar index;
if(DCACHE == 1) begin: readdata
for (index = 0; index < WORDSPERLINE; index++) begin:readdatalinesetsmux
assign ReadDataLineSets[index] = ReadDataLineM[((index+1)*`XLEN)-1: (index*`XLEN)];
end
// variable input mux
assign ReadDataWord = ReadDataLineSets[LsuPAdrM[LOGWPL + LOGXLENBYTES - 1 : LOGXLENBYTES]];
end else begin: readdata
logic [31:0] ReadLineSetsF [LINELEN/16-1:0];
logic [31:0] FinalInstrRawF;
for(index = 0; index < LINELEN / 16 - 1; index++)
assign ReadLineSetsF[index] = ReadDataLineM[((index+1)*16)+16-1 : (index*16)];
assign ReadLineSetsF[LINELEN/16-1] = {16'b0, ReadDataLineM[LINELEN-1:LINELEN-16]};
assign FinalInstrRawF = ReadLineSetsF[LsuPAdrM[$clog2(LINELEN / 32) + 1 : 1]];
if (`XLEN == 64) assign ReadDataWord = {32'b0, FinalInstrRawF};
else assign ReadDataWord = FinalInstrRawF;
end
// Write Path CPU (IEU) side
onehotdecoder #(LOGWPL)
adrdec(.bin(LsuPAdrM[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]),
.decoded(MemPAdrDecodedW));
assign SRAMWordEnable = SRAMLineWriteEnableM ? '1 : MemPAdrDecodedW;
assign SRAMLineWayWriteEnableM = SRAMLineWriteEnableM ? VictimWay : '0;
mux2 #(NUMWAYS) WriteEnableMux(.d0(SRAMWordWriteEnableM ? WayHit : '0),
.d1(SRAMLineWayWriteEnableM),
.s(SRAMLineWriteEnableM),
.y(SRAMWayWriteEnable));
mux2 #(LINELEN) WriteDataMux(.d0({WORDSPERLINE{FinalWriteData}}),
.d1(CacheMemWriteData),
.s(SRAMLineWriteEnableM),
.y(SRAMWriteData));
mux3 #(`PA_BITS) BaseAdrMux(.d0({LsuPAdrM[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
.d1({VictimTag, LsuPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
.d2({VictimTag, FlushAdrQ, {{OFFSETLEN}{1'b0}}}),
.s({SelFlush, SelEvict}),
.y(CacheBusAdr));
// flush address and way generation.
// increment on 2nd to last way
flopenr #(INDEXLEN)
FlushAdrReg(.clk,
.reset(reset | FlushAdrCntRst),
.en(FlushAdrCntEn & FlushWay[NUMWAYS-2]),
.d(FlushAdrP1),
.q(FlushAdr));
assign FlushAdrP1 = FlushAdr + 1'b1;
flopenr #(INDEXLEN)
FlushAdrQReg(.clk,
.reset(reset | FlushAdrCntRst),
.en(FlushAdrCntEn),
.d(FlushAdr),
.q(FlushAdrQ));
flopenl #(NUMWAYS)
FlushWayReg(.clk,
.load(reset | FlushWayCntRst),
.en(FlushWayCntEn),
.val({{NUMWAYS-1{1'b0}}, 1'b1}),
.d(NextFlushWay),
.q(FlushWay));
assign VDWriteEnableWay = FlushWay & {NUMWAYS{VDWriteEnable}};
assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]};
assign FlushAdrFlag = FlushAdr == FlushAdrThreshold[INDEXLEN-1:0] & FlushWay[NUMWAYS-1];
// controller
// *** fixme
logic CacheableM;
assign CacheableM = 1;
cachefsm cachefsm(.clk, .reset, .CacheFetchLine, .CacheWriteLine, .CacheBusAck,
.RW, .Atomic, .CPUBusy, .CacheableM, .IgnoreRequest,
.CacheHit, .VictimDirty, .CacheStall, .CacheCommitted,
.CacheMiss, .CacheAccess, .SelAdrM, .SetValid,
.ClearValid, .SetDirty, .ClearDirty, .SRAMWordWriteEnableM,
.SRAMLineWriteEnableM, .SelEvict, .SelFlush,
.FlushAdrCntEn, .FlushWayCntEn, .FlushAdrCntRst,
.FlushWayCntRst, .FlushAdrFlag, .FlushCache,
.VDWriteEnable, .LRUWriteEn);
endmodule // dcache

398
pipelined/src/cache/cachefsm.sv vendored Normal file
View File

@ -0,0 +1,398 @@
///////////////////////////////////////////
// dcache (data cache) fsm
//
// Written: ross1728@gmail.com August 25, 2021
// Implements the L1 data cache fsm
//
// Purpose: Controller for the dcache fsm
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-config.vh"
module cachefsm
(input logic clk,
input logic reset,
// inputs from IEU
input logic [1:0] RW,
input logic [1:0] Atomic,
input logic FlushCache,
// hazard inputs
input logic CPUBusy,
input logic CacheableM,
// interlock fsm
input logic IgnoreRequest,
// Bus inputs
input logic CacheBusAck,
// dcache internals
input logic CacheHit,
input logic VictimDirty,
input logic FlushAdrFlag,
// hazard outputs
output logic CacheStall,
// counter outputs
output logic CacheMiss,
output logic CacheAccess,
// Bus outputs
output logic CacheCommitted,
output logic CacheWriteLine,
output logic CacheFetchLine,
// dcache internals
output logic [1:0] SelAdrM,
output logic SetValid,
output logic ClearValid,
output logic SetDirty,
output logic ClearDirty,
output logic SRAMWordWriteEnableM,
output logic SRAMLineWriteEnableM,
output logic SelEvict,
output logic LRUWriteEn,
output logic SelFlush,
output logic FlushAdrCntEn,
output logic FlushWayCntEn,
output logic FlushAdrCntRst,
output logic FlushWayCntRst,
output logic VDWriteEnable
);
logic AnyCPUReqM;
typedef enum {STATE_READY,
STATE_MISS_FETCH_WDV,
STATE_MISS_FETCH_DONE,
STATE_MISS_EVICT_DIRTY,
STATE_MISS_WRITE_CACHE_LINE,
STATE_MISS_READ_WORD,
STATE_MISS_READ_WORD_DELAY,
STATE_MISS_WRITE_WORD,
STATE_CPU_BUSY,
STATE_CPU_BUSY_FINISH_AMO,
STATE_FLUSH,
STATE_FLUSH_WRITE_BACK,
STATE_FLUSH_CLEAR_DIRTY} statetype;
(* mark_debug = "true" *) statetype CurrState, NextState;
assign AnyCPUReqM = |RW | (|Atomic);
// outputs for the performance counters.
assign CacheAccess = AnyCPUReqM & CacheableM & CurrState == STATE_READY;
assign CacheMiss = CacheAccess & CacheableM & ~CacheHit;
always_ff @(posedge clk)
if (reset) CurrState <= #1 STATE_READY;
else CurrState <= #1 NextState;
// next state logic and some state ouputs.
always_comb begin
CacheStall = 1'b0;
SelAdrM = 2'b00;
SetValid = 1'b0;
ClearValid = 1'b0;
SetDirty = 1'b0;
ClearDirty = 1'b0;
SRAMWordWriteEnableM = 1'b0;
SRAMLineWriteEnableM = 1'b0;
SelEvict = 1'b0;
LRUWriteEn = 1'b0;
SelFlush = 1'b0;
FlushAdrCntEn = 1'b0;
FlushWayCntEn = 1'b0;
FlushAdrCntRst = 1'b0;
FlushWayCntRst = 1'b0;
VDWriteEnable = 1'b0;
NextState = STATE_READY;
CacheFetchLine = 1'b0;
CacheWriteLine = 1'b0;
case (CurrState)
STATE_READY: begin
CacheStall = 1'b0;
SelAdrM = 2'b00;
SRAMWordWriteEnableM = 1'b0;
SetDirty = 1'b0;
LRUWriteEn = 1'b0;
// TLB Miss
if(IgnoreRequest) begin
// the LSU arbiter has not yet selected the PTW.
// The CPU needs to be stalled until that happens.
// If we set CacheStall for 1 cycle before going to
// PTW ready the CPU will stall.
// The page table walker asserts it's control 1 cycle
// after the TLBs miss.
SelAdrM = 2'b01;
NextState = STATE_READY;
end
// Flush dcache to next level of memory
else if(FlushCache) begin
NextState = STATE_FLUSH;
CacheStall = 1'b1;
SelAdrM = 2'b10;
FlushAdrCntRst = 1'b1;
FlushWayCntRst = 1'b1;
end
// amo hit
else if(Atomic[1] & (&RW) & CacheableM & CacheHit) begin
SelAdrM = 2'b01;
CacheStall = 1'b0;
if(CPUBusy) begin
NextState = STATE_CPU_BUSY_FINISH_AMO;
SelAdrM = 2'b01;
end
else begin
SRAMWordWriteEnableM = 1'b1;
SetDirty = 1'b1;
LRUWriteEn = 1'b1;
NextState = STATE_READY;
end
end
// read hit valid cached
else if(RW[1] & CacheableM & CacheHit) begin
CacheStall = 1'b0;
LRUWriteEn = 1'b1;
if(CPUBusy) begin
NextState = STATE_CPU_BUSY;
SelAdrM = 2'b01;
end
else begin
NextState = STATE_READY;
end
end
// write hit valid cached
else if (RW[0] & CacheableM & CacheHit) begin
SelAdrM = 2'b01;
CacheStall = 1'b0;
SRAMWordWriteEnableM = 1'b1;
SetDirty = 1'b1;
LRUWriteEn = 1'b1;
if(CPUBusy) begin
NextState = STATE_CPU_BUSY;
SelAdrM = 2'b01;
end
else begin
NextState = STATE_READY;
end
end
// read or write miss valid cached
else if((|RW) & CacheableM & ~CacheHit) begin
NextState = STATE_MISS_FETCH_WDV;
CacheStall = 1'b1;
CacheFetchLine = 1'b1;
end
else NextState = STATE_READY;
end
STATE_MISS_FETCH_WDV: begin
CacheStall = 1'b1;
SelAdrM = 2'b01;
if (CacheBusAck) begin
NextState = STATE_MISS_FETCH_DONE;
end else begin
NextState = STATE_MISS_FETCH_WDV;
end
end
STATE_MISS_FETCH_DONE: begin
CacheStall = 1'b1;
SelAdrM = 2'b01;
if(VictimDirty) begin
NextState = STATE_MISS_EVICT_DIRTY;
CacheWriteLine = 1'b1;
end else begin
NextState = STATE_MISS_WRITE_CACHE_LINE;
end
end
STATE_MISS_WRITE_CACHE_LINE: begin
SRAMLineWriteEnableM = 1'b1;
CacheStall = 1'b1;
NextState = STATE_MISS_READ_WORD;
SelAdrM = 2'b01;
SetValid = 1'b1;
ClearDirty = 1'b1;
//LRUWriteEn = 1'b1; // DO not update LRU on SRAM fetch update. Wait for subsequent read/write
end
STATE_MISS_READ_WORD: begin
SelAdrM = 2'b01;
CacheStall = 1'b1;
if (RW[0] & ~Atomic[1]) begin // handles stores and amo write.
NextState = STATE_MISS_WRITE_WORD;
end else begin
NextState = STATE_MISS_READ_WORD_DELAY;
// delay state is required as the read signal RW[1] is still high when we
// return to the ready state because the cache is stalling the cpu.
end
end
STATE_MISS_READ_WORD_DELAY: begin
//SelAdrM = 2'b01;
SRAMWordWriteEnableM = 1'b0;
SetDirty = 1'b0;
LRUWriteEn = 1'b0;
if(&RW & Atomic[1]) begin // amo write
SelAdrM = 2'b01;
if(CPUBusy) begin
NextState = STATE_CPU_BUSY_FINISH_AMO;
end
else begin
SRAMWordWriteEnableM = 1'b1;
SetDirty = 1'b1;
LRUWriteEn = 1'b1;
NextState = STATE_READY;
end
end else begin
LRUWriteEn = 1'b1;
if(CPUBusy) begin
NextState = STATE_CPU_BUSY;
SelAdrM = 2'b01;
end
else begin
NextState = STATE_READY;
end
end
end
STATE_MISS_WRITE_WORD: begin
SRAMWordWriteEnableM = 1'b1;
SetDirty = 1'b1;
SelAdrM = 2'b01;
LRUWriteEn = 1'b1;
if(CPUBusy) begin
NextState = STATE_CPU_BUSY;
SelAdrM = 2'b01;
end
else begin
NextState = STATE_READY;
end
end
STATE_MISS_EVICT_DIRTY: begin
CacheStall = 1'b1;
SelAdrM = 2'b01;
SelEvict = 1'b1;
if(CacheBusAck) begin
NextState = STATE_MISS_WRITE_CACHE_LINE;
end else begin
NextState = STATE_MISS_EVICT_DIRTY;
end
end
STATE_CPU_BUSY: begin
SelAdrM = 2'b00;
if(CPUBusy) begin
NextState = STATE_CPU_BUSY;
SelAdrM = 2'b01;
end
else begin
NextState = STATE_READY;
end
end
STATE_CPU_BUSY_FINISH_AMO: begin
SelAdrM = 2'b01;
SRAMWordWriteEnableM = 1'b0;
SetDirty = 1'b0;
LRUWriteEn = 1'b0;
if(CPUBusy) begin
NextState = STATE_CPU_BUSY_FINISH_AMO;
end
else begin
SRAMWordWriteEnableM = 1'b1;
SetDirty = 1'b1;
LRUWriteEn = 1'b1;
NextState = STATE_READY;
end
end
STATE_FLUSH: begin
CacheStall = 1'b1;
SelAdrM = 2'b10;
SelFlush = 1'b1;
FlushAdrCntEn = 1'b1;
FlushWayCntEn = 1'b1;
if(VictimDirty) begin
NextState = STATE_FLUSH_WRITE_BACK;
FlushAdrCntEn = 1'b0;
FlushWayCntEn = 1'b0;
CacheWriteLine = 1'b1;
end else if (FlushAdrFlag) begin
NextState = STATE_READY;
CacheStall = 1'b0;
FlushAdrCntEn = 1'b0;
FlushWayCntEn = 1'b0;
end else begin
NextState = STATE_FLUSH;
end
end
STATE_FLUSH_WRITE_BACK: begin
CacheStall = 1'b1;
SelAdrM = 2'b10;
SelFlush = 1'b1;
if(CacheBusAck) begin
NextState = STATE_FLUSH_CLEAR_DIRTY;
end else begin
NextState = STATE_FLUSH_WRITE_BACK;
end
end
STATE_FLUSH_CLEAR_DIRTY: begin
CacheStall = 1'b1;
ClearDirty = 1'b1;
VDWriteEnable = 1'b1;
SelFlush = 1'b1;
SelAdrM = 2'b10;
FlushAdrCntEn = 1'b0;
FlushWayCntEn = 1'b0;
if(FlushAdrFlag) begin
NextState = STATE_READY;
CacheStall = 1'b0;
SelAdrM = 2'b00;
end else begin
NextState = STATE_FLUSH;
FlushAdrCntEn = 1'b1;
FlushWayCntEn = 1'b1;
end
end
default: begin
NextState = STATE_READY;
end
endcase
end
assign CacheCommitted = CurrState != STATE_READY;
endmodule // cachefsm

39
pipelined/src/cache/cachereplacementpolicy.sv vendored
View File

@ -40,7 +40,7 @@ module cachereplacementpolicy
logic [NUMWAYS-2:0] LRUEn, LRUMask; logic [NUMWAYS-2:0] LRUEn, LRUMask;
logic [$clog2(NUMWAYS)-1:0] EncVicWay; logic [$clog2(NUMWAYS)-1:0] EncVicWay;
logic [NUMWAYS-2:0] ReplacementBits [NUMLINES-1:0]; logic [NUMWAYS-2:0] ReplacementBits [NUMLINES-1:0];
logic [NUMWAYS-2:0] BlockReplacementBits; logic [NUMWAYS-2:0] LineReplacementBits;
logic [NUMWAYS-2:0] NewReplacement; logic [NUMWAYS-2:0] NewReplacement;
logic [NUMWAYS-2:0] NewReplacementD; logic [NUMWAYS-2:0] NewReplacementD;
@ -69,26 +69,25 @@ module cachereplacementpolicy
end end
/* verilator lint_on BLKLOOPINIT */ /* verilator lint_on BLKLOOPINIT */
assign BlockReplacementBits = ReplacementBits[RAdrD]; assign LineReplacementBits = ReplacementBits[RAdrD];
genvar index; genvar index;
generate
if(NUMWAYS == 2) begin : TwoWay if(NUMWAYS == 2) begin : TwoWay
assign LRUEn[0] = 1'b0; assign LRUEn[0] = 1'b0;
assign NewReplacement[0] = WayHit[1]; assign NewReplacement[0] = WayHit[1];
assign VictimWay[1] = ~BlockReplacementBits[0]; assign VictimWay[1] = ~LineReplacementBits[0];
assign VictimWay[0] = BlockReplacementBits[0]; assign VictimWay[0] = LineReplacementBits[0];
end else if (NUMWAYS == 4) begin : FourWay end else if (NUMWAYS == 4) begin : FourWay
// VictimWay is a function only of the current value of the LRU. // VictimWay is a function only of the current value of the LRU.
// binary encoding // binary encoding
//assign VictimWay[0] = BlockReplacementBits[2] ? BlockReplacementBits[1] : BlockReplacementBits[0]; //assign VictimWay[0] = LineReplacementBits[2] ? LineReplacementBits[1] : LineReplacementBits[0];
//assign VictimWay[1] = BlockReplacementBits[2]; //assign VictimWay[1] = LineReplacementBits[2];
// 1 hot encoding // 1 hot encoding
//| WayHit | LRU 2 | LRU 1 | LRU 0 | //| WayHit | LRU 2 | LRU 1 | LRU 0 |
@ -99,10 +98,10 @@ module cachereplacementpolicy
//| 0100 | 0 | 1 | - | //| 0100 | 0 | 1 | - |
//| 1000 | 0 | 0 | - | //| 1000 | 0 | 0 | - |
assign VictimWay[0] = ~BlockReplacementBits[2] & ~BlockReplacementBits[0]; assign VictimWay[0] = ~LineReplacementBits[2] & ~LineReplacementBits[0];
assign VictimWay[1] = ~BlockReplacementBits[2] & BlockReplacementBits[0]; assign VictimWay[1] = ~LineReplacementBits[2] & LineReplacementBits[0];
assign VictimWay[2] = BlockReplacementBits[2] & ~BlockReplacementBits[1]; assign VictimWay[2] = LineReplacementBits[2] & ~LineReplacementBits[1];
assign VictimWay[3] = BlockReplacementBits[2] & BlockReplacementBits[1]; assign VictimWay[3] = LineReplacementBits[2] & LineReplacementBits[1];
// New LRU bits which are updated is function only of the WayHit. // New LRU bits which are updated is function only of the WayHit.
// However the not updated bits come from the old LRU. // However the not updated bits come from the old LRU.
@ -128,11 +127,11 @@ module cachereplacementpolicy
-----/\----- EXCLUDED -----/\----- */ -----/\----- EXCLUDED -----/\----- */
for(index = 0; index < NUMWAYS-1; index++) for(index = 0; index < NUMWAYS-1; index++)
assign NewReplacement[index] = LRUEn[index] ? LRUMask[index] : BlockReplacementBits[index]; assign NewReplacement[index] = LRUEn[index] ? LRUMask[index] : LineReplacementBits[index];
/* -----\/----- EXCLUDED -----\/----- /* -----\/----- EXCLUDED -----\/-----
assign EncVicWay[1] = BlockReplacementBits[2]; assign EncVicWay[1] = LineReplacementBits[2];
assign EncVicWay[0] = BlockReplacementBits[2] ? BlockReplacementBits[0] : BlockReplacementBits[1]; assign EncVicWay[0] = LineReplacementBits[2] ? LineReplacementBits[0] : LineReplacementBits[1];
onehotdecoder #(2) onehotdecoder #(2)
waydec(.bin(EncVicWay), waydec(.bin(EncVicWay),
@ -160,12 +159,12 @@ module cachereplacementpolicy
assign LRUMask[0] = WayHit[0]; assign LRUMask[0] = WayHit[0];
for(index = 0; index < NUMWAYS-1; index++) for(index = 0; index < NUMWAYS-1; index++)
assign NewReplacement[index] = LRUEn[index] ? LRUMask[index] : BlockReplacementBits[index]; assign NewReplacement[index] = LRUEn[index] ? LRUMask[index] : LineReplacementBits[index];
assign EncVicWay[2] = BlockReplacementBits[6]; assign EncVicWay[2] = LineReplacementBits[6];
assign EncVicWay[1] = BlockReplacementBits[6] ? BlockReplacementBits[5] : BlockReplacementBits[2]; assign EncVicWay[1] = LineReplacementBits[6] ? LineReplacementBits[5] : LineReplacementBits[2];
assign EncVicWay[0] = BlockReplacementBits[6] ? BlockReplacementBits[5] ? BlockReplacementBits[4] : BlockReplacementBits[3] : assign EncVicWay[0] = LineReplacementBits[6] ? LineReplacementBits[5] ? LineReplacementBits[4] : LineReplacementBits[3] :
BlockReplacementBits[2] ? BlockReplacementBits[1] : BlockReplacementBits[0]; LineReplacementBits[2] ? LineReplacementBits[1] : LineReplacementBits[0];
onehotdecoder #(3) onehotdecoder #(3)
@ -173,8 +172,6 @@ module cachereplacementpolicy
.decoded({VictimWay[0], VictimWay[1], VictimWay[2], VictimWay[3], .decoded({VictimWay[0], VictimWay[1], VictimWay[2], VictimWay[3],
VictimWay[4], VictimWay[5], VictimWay[6], VictimWay[7]})); VictimWay[4], VictimWay[5], VictimWay[6], VictimWay[7]}));
end end
endgenerate
endmodule endmodule

29
pipelined/src/cache/cacheway.sv vendored
View File

@ -25,7 +25,7 @@
`include "wally-config.vh" `include "wally-config.vh"
module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26, module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
parameter OFFSETLEN = 5, parameter INDEXLEN = 9, parameter DIRTY_BITS = 1) parameter OFFSETLEN = 5, parameter INDEXLEN = 9, parameter DIRTY_BITS = 1)
(input logic clk, (input logic clk,
input logic reset, input logic reset,
@ -34,9 +34,9 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
input logic [`PA_BITS-1:0] PAdr, input logic [`PA_BITS-1:0] PAdr,
input logic WriteEnable, input logic WriteEnable,
input logic VDWriteEnable, input logic VDWriteEnable,
input logic [BLOCKLEN/`XLEN-1:0] WriteWordEnable, input logic [LINELEN/`XLEN-1:0] WriteWordEnable,
input logic TagWriteEnable, input logic TagWriteEnable,
input logic [BLOCKLEN-1:0] WriteData, input logic [LINELEN-1:0] WriteData,
input logic SetValid, input logic SetValid,
input logic ClearValid, input logic ClearValid,
input logic SetDirty, input logic SetDirty,
@ -47,7 +47,7 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
input logic SelFlush, input logic SelFlush,
input logic FlushWay, input logic FlushWay,
output logic [BLOCKLEN-1:0] ReadDataLineWayMasked, output logic [LINELEN-1:0] ReadDataLineWayMasked,
output logic WayHit, output logic WayHit,
output logic VictimDirtyWay, output logic VictimDirtyWay,
output logic [TAGLEN-1:0] VictimTagWay output logic [TAGLEN-1:0] VictimTagWay
@ -55,7 +55,7 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
logic [NUMLINES-1:0] ValidBits; logic [NUMLINES-1:0] ValidBits;
logic [NUMLINES-1:0] DirtyBits; logic [NUMLINES-1:0] DirtyBits;
logic [BLOCKLEN-1:0] ReadDataBlockWay; logic [LINELEN-1:0] ReadDataLineWay;
logic [TAGLEN-1:0] ReadTag; logic [TAGLEN-1:0] ReadTag;
logic Valid; logic Valid;
logic Dirty; logic Dirty;
@ -72,16 +72,13 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
genvar words; genvar words;
for(words = 0; words < LINELEN/`XLEN; words++) begin: word
generate
for(words = 0; words < BLOCKLEN/`XLEN; words++) begin : word
sram1rw #(.DEPTH(`XLEN), .WIDTH(NUMLINES)) sram1rw #(.DEPTH(`XLEN), .WIDTH(NUMLINES))
CacheDataMem(.clk(clk), .Addr(RAdr), CacheDataMem(.clk(clk), .Addr(RAdr),
.ReadData(ReadDataBlockWay[(words+1)*`XLEN-1:words*`XLEN] ), .ReadData(ReadDataLineWay[(words+1)*`XLEN-1:words*`XLEN] ),
.WriteData(WriteData[(words+1)*`XLEN-1:words*`XLEN]), .WriteData(WriteData[(words+1)*`XLEN-1:words*`XLEN]),
.WriteEnable(WriteEnable & WriteWordEnable[words])); .WriteEnable(WriteEnable & WriteWordEnable[words]));
end end
endgenerate
sram1rw #(.DEPTH(TAGLEN), .WIDTH(NUMLINES)) sram1rw #(.DEPTH(TAGLEN), .WIDTH(NUMLINES))
CacheTagMem(.clk(clk), CacheTagMem(.clk(clk),
@ -93,7 +90,7 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
assign WayHit = Valid & (ReadTag == PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]); assign WayHit = Valid & (ReadTag == PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]);
assign SelectedWay = SelFlush ? FlushWay : assign SelectedWay = SelFlush ? FlushWay :
SelEvict ? VictimWay : WayHit; SelEvict ? VictimWay : WayHit;
assign ReadDataLineWayMasked = SelectedWay ? ReadDataBlockWay : '0; // first part of AO mux. assign ReadDataLineWayMasked = SelectedWay ? ReadDataLineWay : '0; // first part of AO mux.
assign VictimDirtyWay = SelFlush ? FlushWay & Dirty & Valid : assign VictimDirtyWay = SelFlush ? FlushWay & Dirty & Valid :
VictimWay & Dirty & Valid; VictimWay & Dirty & Valid;
@ -123,27 +120,21 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
assign Valid = ValidBits[RAdrD]; assign Valid = ValidBits[RAdrD];
generate // Dirty bits
if(DIRTY_BITS) begin:dirty if(DIRTY_BITS) begin:dirty
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
if (reset) if (reset) DirtyBits <= {NUMLINES{1'b0}};
DirtyBits <= {NUMLINES{1'b0}};
else if (SetDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[RAdrD] <= 1'b1; else if (SetDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[RAdrD] <= 1'b1;
else if (ClearDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[RAdrD] <= 1'b0; else if (ClearDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[RAdrD] <= 1'b0;
end end
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
SetDirtyD <= SetDirty; SetDirtyD <= SetDirty;
ClearDirtyD <= ClearDirty; ClearDirtyD <= ClearDirty;
end end
assign Dirty = DirtyBits[RAdrD]; assign Dirty = DirtyBits[RAdrD];
end else begin:dirty end else begin:dirty
assign Dirty = 1'b0; assign Dirty = 1'b0;
end end
endgenerate
endmodule // DCacheMemWay endmodule // DCacheMemWay

74
pipelined/src/cache/dcache.sv vendored
View File

@ -25,7 +25,9 @@
`include "wally-config.vh" `include "wally-config.vh"
module dcache module dcache #(parameter integer LINELEN,
parameter integer NUMLINES,
parameter integer NUMWAYS)
(input logic clk, (input logic clk,
input logic reset, input logic reset,
input logic CPUBusy, input logic CPUBusy,
@ -52,8 +54,8 @@ module dcache
output logic [`PA_BITS-1:0] DCacheBusAdr, output logic [`PA_BITS-1:0] DCacheBusAdr,
input logic [`DCACHE_BLOCKLENINBITS-1:0] DCacheMemWriteData, input logic [LINELEN-1:0] DCacheMemWriteData,
output logic [`XLEN-1:0] ReadDataBlockSetsM [(`DCACHE_BLOCKLENINBITS/`XLEN)-1:0], output logic [`XLEN-1:0] ReadDataLineSetsM [(LINELEN/`XLEN)-1:0],
output logic DCacheStall, output logic DCacheStall,
@ -62,34 +64,31 @@ module dcache
output logic DCacheAccess output logic DCacheAccess
); );
localparam integer BLOCKLEN = `DCACHE_BLOCKLENINBITS;
localparam integer NUMLINES = `DCACHE_WAYSIZEINBYTES*8/BLOCKLEN;
localparam integer NUMWAYS = `DCACHE_NUMWAYS;
localparam integer BLOCKBYTELEN = BLOCKLEN/8; localparam integer LINEBYTELEN = LINELEN/8;
localparam integer OFFSETLEN = $clog2(BLOCKBYTELEN); localparam integer OFFSETLEN = $clog2(LINEBYTELEN);
localparam integer INDEXLEN = $clog2(NUMLINES); localparam integer INDEXLEN = $clog2(NUMLINES);
localparam integer TAGLEN = `PA_BITS - OFFSETLEN - INDEXLEN; localparam integer TAGLEN = `PA_BITS - OFFSETLEN - INDEXLEN;
localparam integer WORDSPERLINE = BLOCKLEN/`XLEN; localparam integer WORDSPERLINE = LINELEN/`XLEN;
localparam integer LOGWPL = $clog2(WORDSPERLINE); localparam integer LOGWPL = $clog2(WORDSPERLINE);
localparam integer LOGXLENBYTES = $clog2(`XLEN/8); localparam integer LOGXLENBYTES = $clog2(`XLEN/8);
localparam integer FlushAdrThreshold = NUMLINES - 1; localparam integer FlushAdrThreshold = NUMLINES;
logic [1:0] SelAdrM; logic [1:0] SelAdrM;
logic [INDEXLEN-1:0] RAdr; logic [INDEXLEN-1:0] RAdr;
logic [BLOCKLEN-1:0] SRAMWriteData; logic [LINELEN-1:0] SRAMWriteData;
logic SetValid, ClearValid; logic SetValid, ClearValid;
logic SetDirty, ClearDirty; logic SetDirty, ClearDirty;
logic [BLOCKLEN-1:0] ReadDataLineWayMasked [NUMWAYS-1:0]; logic [LINELEN-1:0] ReadDataLineWayMasked [NUMWAYS-1:0];
logic [NUMWAYS-1:0] WayHit; logic [NUMWAYS-1:0] WayHit;
logic CacheHit; logic CacheHit;
logic [BLOCKLEN-1:0] ReadDataLineM; logic [LINELEN-1:0] ReadDataLineM;
logic [WORDSPERLINE-1:0] SRAMWordEnable; logic [WORDSPERLINE-1:0] SRAMWordEnable;
logic SRAMWordWriteEnableM; logic SRAMWordWriteEnableM;
logic SRAMBlockWriteEnableM; logic SRAMLineWriteEnableM;
logic [NUMWAYS-1:0] SRAMBlockWayWriteEnableM; logic [NUMWAYS-1:0] SRAMLineWayWriteEnableM;
logic [NUMWAYS-1:0] SRAMWayWriteEnable; logic [NUMWAYS-1:0] SRAMWayWriteEnable;
@ -104,6 +103,7 @@ module dcache
logic [INDEXLEN-1:0] FlushAdr; logic [INDEXLEN-1:0] FlushAdr;
logic [INDEXLEN-1:0] FlushAdrP1; logic [INDEXLEN-1:0] FlushAdrP1;
logic [INDEXLEN-1:0] FlushAdrQ;
logic FlushAdrCntEn; logic FlushAdrCntEn;
logic FlushAdrCntRst; logic FlushAdrCntRst;
logic FlushAdrFlag; logic FlushAdrFlag;
@ -128,14 +128,14 @@ module dcache
.s(SelAdrM), .s(SelAdrM),
.y(RAdr)); .y(RAdr));
cacheway #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN), cacheway #(.NUMLINES(NUMLINES), .LINELEN(LINELEN), .TAGLEN(TAGLEN),
.OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN)) .OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN))
MemWay[NUMWAYS-1:0](.clk, .reset, .RAdr, MemWay[NUMWAYS-1:0](.clk, .reset, .RAdr,
.PAdr(LsuPAdrM), .PAdr(LsuPAdrM),
.WriteEnable(SRAMWayWriteEnable), .WriteEnable(SRAMWayWriteEnable),
.VDWriteEnable(VDWriteEnableWay), .VDWriteEnable(VDWriteEnableWay),
.WriteWordEnable(SRAMWordEnable), .WriteWordEnable(SRAMWordEnable),
.TagWriteEnable(SRAMBlockWayWriteEnableM), .TagWriteEnable(SRAMLineWayWriteEnableM),
.WriteData(SRAMWriteData), .WriteData(SRAMWriteData),
.SetValid, .ClearValid, .SetDirty, .ClearDirty, .SelEvict, .SetValid, .ClearValid, .SetDirty, .ClearDirty, .SelEvict,
.VictimWay, .FlushWay, .SelFlush, .VictimWay, .FlushWay, .SelFlush,
@ -143,7 +143,6 @@ module dcache
.WayHit, .VictimDirtyWay, .VictimTagWay, .WayHit, .VictimDirtyWay, .VictimTagWay,
.InvalidateAll(1'b0)); .InvalidateAll(1'b0));
generate
if(NUMWAYS > 1) begin:vict if(NUMWAYS > 1) begin:vict
cachereplacementpolicy #(NUMWAYS, INDEXLEN, OFFSETLEN, NUMLINES) cachereplacementpolicy #(NUMWAYS, INDEXLEN, OFFSETLEN, NUMLINES)
cachereplacementpolicy(.clk, .reset, cachereplacementpolicy(.clk, .reset,
@ -155,16 +154,15 @@ module dcache
end else begin:vict end else begin:vict
assign VictimWay = 1'b1; // one hot. assign VictimWay = 1'b1; // one hot.
end end
endgenerate
assign CacheHit = | WayHit; assign CacheHit = | WayHit;
assign VictimDirty = | VictimDirtyWay; assign VictimDirty = | VictimDirtyWay;
// ReadDataLineWayMaskedM is a 2d array of cache block len by number of ways. // ReadDataLineWayMaskedM is a 2d array of cache line len by number of ways.
// Need to OR together each way in a bitwise manner. // Need to OR together each way in a bitwise manner.
// Final part of the AO Mux. First is the AND in the cacheway. // Final part of the AO Mux. First is the AND in the cacheway.
or_rows #(NUMWAYS, BLOCKLEN) ReadDataAOMux(.a(ReadDataLineWayMasked), .y(ReadDataLineM)); or_rows #(NUMWAYS, LINELEN) ReadDataAOMux(.a(ReadDataLineWayMasked), .y(ReadDataLineM));
or_rows #(NUMWAYS, TAGLEN) VictimTagAOMux(.a(VictimTagWay), .y(VictimTag)); or_rows #(NUMWAYS, TAGLEN) VictimTagAOMux(.a(VictimTagWay), .y(VictimTag));
@ -172,15 +170,12 @@ module dcache
// easily build a variable input mux. // easily build a variable input mux.
// *** consider using a limited range shift to do this final muxing. // *** consider using a limited range shift to do this final muxing.
genvar index; genvar index;
generate for (index = 0; index < WORDSPERLINE; index++)
for (index = 0; index < WORDSPERLINE; index++) begin:readdatablocksetsmux assign ReadDataLineSetsM[index] = ReadDataLineM[((index+1)*`XLEN)-1: (index*`XLEN)];
assign ReadDataBlockSetsM[index] = ReadDataLineM[((index+1)*`XLEN)-1: (index*`XLEN)];
end
endgenerate
// variable input mux // variable input mux
assign ReadDataWordM = ReadDataBlockSetsM[LsuPAdrM[LOGWPL + LOGXLENBYTES - 1 : LOGXLENBYTES]]; assign ReadDataWordM = ReadDataLineSetsM[LsuPAdrM[LOGWPL + LOGXLENBYTES - 1 : LOGXLENBYTES]];
// Write Path CPU (IEU) side // Write Path CPU (IEU) side
@ -188,39 +183,46 @@ module dcache
adrdec(.bin(LsuPAdrM[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), adrdec(.bin(LsuPAdrM[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]),
.decoded(MemPAdrDecodedW)); .decoded(MemPAdrDecodedW));
assign SRAMWordEnable = SRAMBlockWriteEnableM ? '1 : MemPAdrDecodedW; assign SRAMWordEnable = SRAMLineWriteEnableM ? '1 : MemPAdrDecodedW;
assign SRAMBlockWayWriteEnableM = SRAMBlockWriteEnableM ? VictimWay : '0; assign SRAMLineWayWriteEnableM = SRAMLineWriteEnableM ? VictimWay : '0;
mux2 #(NUMWAYS) WriteEnableMux(.d0(SRAMWordWriteEnableM ? WayHit : '0), mux2 #(NUMWAYS) WriteEnableMux(.d0(SRAMWordWriteEnableM ? WayHit : '0),
.d1(SRAMBlockWayWriteEnableM), .d1(SRAMLineWayWriteEnableM),
.s(SRAMBlockWriteEnableM), .s(SRAMLineWriteEnableM),
.y(SRAMWayWriteEnable)); .y(SRAMWayWriteEnable));
mux2 #(BLOCKLEN) WriteDataMux(.d0({WORDSPERLINE{FinalWriteDataM}}), mux2 #(LINELEN) WriteDataMux(.d0({WORDSPERLINE{FinalWriteDataM}}),
.d1(DCacheMemWriteData), .d1(DCacheMemWriteData),
.s(SRAMBlockWriteEnableM), .s(SRAMLineWriteEnableM),
.y(SRAMWriteData)); .y(SRAMWriteData));
mux3 #(`PA_BITS) BaseAdrMux(.d0({LsuPAdrM[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), mux3 #(`PA_BITS) BaseAdrMux(.d0({LsuPAdrM[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
.d1({VictimTag, LsuPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), .d1({VictimTag, LsuPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
.d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}), .d2({VictimTag, FlushAdrQ, {{OFFSETLEN}{1'b0}}}),
.s({SelFlush, SelEvict}), .s({SelFlush, SelEvict}),
.y(DCacheBusAdr)); .y(DCacheBusAdr));
// flush address and way generation. // flush address and way generation.
// increment on 2nd to last way
flopenr #(INDEXLEN) flopenr #(INDEXLEN)
FlushAdrReg(.clk, FlushAdrReg(.clk,
.reset(reset | FlushAdrCntRst), .reset(reset | FlushAdrCntRst),
.en(FlushAdrCntEn & FlushWay[NUMWAYS-1]), .en(FlushAdrCntEn & FlushWay[NUMWAYS-2]),
.d(FlushAdrP1), .d(FlushAdrP1),
.q(FlushAdr)); .q(FlushAdr));
assign FlushAdrP1 = FlushAdr + 1'b1; assign FlushAdrP1 = FlushAdr + 1'b1;
flopenr #(INDEXLEN)
FlushAdrQReg(.clk,
.reset(reset | FlushAdrCntRst),
.en(FlushAdrCntEn),
.d(FlushAdr),
.q(FlushAdrQ));
flopenl #(NUMWAYS) flopenl #(NUMWAYS)
FlushWayReg(.clk, FlushWayReg(.clk,
@ -243,7 +245,7 @@ module dcache
.CacheHit, .VictimDirty, .DCacheStall, .DCacheCommittedM, .CacheHit, .VictimDirty, .DCacheStall, .DCacheCommittedM,
.DCacheMiss, .DCacheAccess, .SelAdrM, .SetValid, .DCacheMiss, .DCacheAccess, .SelAdrM, .SetValid,
.ClearValid, .SetDirty, .ClearDirty, .SRAMWordWriteEnableM, .ClearValid, .SetDirty, .ClearDirty, .SRAMWordWriteEnableM,
.SRAMBlockWriteEnableM, .SelEvict, .SelFlush, .SRAMLineWriteEnableM, .SelEvict, .SelFlush,
.FlushAdrCntEn, .FlushWayCntEn, .FlushAdrCntRst, .FlushAdrCntEn, .FlushWayCntEn, .FlushAdrCntRst,
.FlushWayCntRst, .FlushAdrFlag, .FlushDCacheM, .FlushWayCntRst, .FlushAdrFlag, .FlushDCacheM,
.VDWriteEnable, .LRUWriteEn); .VDWriteEnable, .LRUWriteEn);

14
pipelined/src/cache/dcachefsm.sv vendored
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@ -61,7 +61,7 @@ module dcachefsm
output logic SetDirty, output logic SetDirty,
output logic ClearDirty, output logic ClearDirty,
output logic SRAMWordWriteEnableM, output logic SRAMWordWriteEnableM,
output logic SRAMBlockWriteEnableM, output logic SRAMLineWriteEnableM,
output logic SelEvict, output logic SelEvict,
output logic LRUWriteEn, output logic LRUWriteEn,
output logic SelFlush, output logic SelFlush,
@ -80,7 +80,7 @@ module dcachefsm
STATE_MISS_FETCH_WDV, STATE_MISS_FETCH_WDV,
STATE_MISS_FETCH_DONE, STATE_MISS_FETCH_DONE,
STATE_MISS_EVICT_DIRTY, STATE_MISS_EVICT_DIRTY,
STATE_MISS_WRITE_CACHE_BLOCK, STATE_MISS_WRITE_CACHE_LINE,
STATE_MISS_READ_WORD, STATE_MISS_READ_WORD,
STATE_MISS_READ_WORD_DELAY, STATE_MISS_READ_WORD_DELAY,
STATE_MISS_WRITE_WORD, STATE_MISS_WRITE_WORD,
@ -113,7 +113,7 @@ module dcachefsm
SetDirty = 1'b0; SetDirty = 1'b0;
ClearDirty = 1'b0; ClearDirty = 1'b0;
SRAMWordWriteEnableM = 1'b0; SRAMWordWriteEnableM = 1'b0;
SRAMBlockWriteEnableM = 1'b0; SRAMLineWriteEnableM = 1'b0;
SelEvict = 1'b0; SelEvict = 1'b0;
LRUWriteEn = 1'b0; LRUWriteEn = 1'b0;
SelFlush = 1'b0; SelFlush = 1'b0;
@ -228,12 +228,12 @@ module dcachefsm
NextState = STATE_MISS_EVICT_DIRTY; NextState = STATE_MISS_EVICT_DIRTY;
DCacheWriteLine = 1'b1; DCacheWriteLine = 1'b1;
end else begin end else begin
NextState = STATE_MISS_WRITE_CACHE_BLOCK; NextState = STATE_MISS_WRITE_CACHE_LINE;
end end
end end
STATE_MISS_WRITE_CACHE_BLOCK: begin STATE_MISS_WRITE_CACHE_LINE: begin
SRAMBlockWriteEnableM = 1'b1; SRAMLineWriteEnableM = 1'b1;
DCacheStall = 1'b1; DCacheStall = 1'b1;
NextState = STATE_MISS_READ_WORD; NextState = STATE_MISS_READ_WORD;
SelAdrM = 2'b01; SelAdrM = 2'b01;
@ -301,7 +301,7 @@ module dcachefsm
SelAdrM = 2'b01; SelAdrM = 2'b01;
SelEvict = 1'b1; SelEvict = 1'b1;
if(DCacheBusAck) begin if(DCacheBusAck) begin
NextState = STATE_MISS_WRITE_CACHE_BLOCK; NextState = STATE_MISS_WRITE_CACHE_LINE;
end else begin end else begin
NextState = STATE_MISS_EVICT_DIRTY; NextState = STATE_MISS_EVICT_DIRTY;
end end

42
pipelined/src/cache/icache.sv vendored
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@ -25,14 +25,15 @@
`include "wally-config.vh" `include "wally-config.vh"
module icache module icache #(parameter integer LINELEN,
parameter integer NUMLINES,
parameter integer NUMWAYS)
( (
// Basic pipeline stuff // Basic pipeline stuff
input logic clk, reset, input logic clk, reset,
input logic CPUBusy, input logic CPUBusy,
// mmu // mmu
//input logic CacheableF,
input logic [1:0] IfuRWF, input logic [1:0] IfuRWF,
// cpu side // cpu side
@ -43,7 +44,7 @@ module icache
// bus fsm interface // bus fsm interface
input logic IgnoreRequest, input logic IgnoreRequest,
input logic [`ICACHE_BLOCKLENINBITS-1:0] ICacheMemWriteData, input logic [LINELEN-1:0] ICacheMemWriteData,
output logic ICacheFetchLine, output logic ICacheFetchLine,
(* mark_debug = "true" *) input logic ICacheBusAck, (* mark_debug = "true" *) input logic ICacheBusAck,
@ -57,25 +58,23 @@ module icache
); );
// Configuration parameters // Configuration parameters
localparam integer BLOCKLEN = `ICACHE_BLOCKLENINBITS; localparam integer LINEBYTELEN = LINELEN/8;
localparam integer NUMLINES = `ICACHE_WAYSIZEINBYTES*8/`ICACHE_BLOCKLENINBITS;
localparam integer BLOCKBYTELEN = BLOCKLEN/8;
localparam integer OFFSETLEN = $clog2(BLOCKBYTELEN); localparam integer OFFSETLEN = $clog2(LINEBYTELEN);
localparam integer INDEXLEN = $clog2(NUMLINES); localparam integer INDEXLEN = $clog2(NUMLINES);
localparam integer TAGLEN = `PA_BITS - OFFSETLEN - INDEXLEN; localparam integer TAGLEN = `PA_BITS - OFFSETLEN - INDEXLEN;
// *** not used? // *** not used?
localparam WORDSPERLINE = BLOCKLEN/`XLEN; localparam WORDSPERLINE = LINELEN/`XLEN;
localparam LOGWPL = $clog2(WORDSPERLINE); localparam LOGWPL = $clog2(WORDSPERLINE);
localparam integer NUMWAYS = `ICACHE_NUMWAYS;
// Input signals to cache memory // Input signals to cache memory
logic ICacheMemWriteEnable; logic ICacheMemWriteEnable;
// Output signals from cache memory // Output signals from cache memory
logic [BLOCKLEN-1:0] ReadLineF; logic [LINELEN-1:0] ReadLineF;
logic SelAdr; logic SelAdr;
logic [INDEXLEN-1:0] RAdr; logic [INDEXLEN-1:0] RAdr;
logic [NUMWAYS-1:0] VictimWay; logic [NUMWAYS-1:0] VictimWay;
@ -84,9 +83,9 @@ module icache
logic hit; logic hit;
logic [BLOCKLEN-1:0] ReadDataLineWayMasked [NUMWAYS-1:0]; logic [LINELEN-1:0] ReadDataLineWayMasked [NUMWAYS-1:0];
logic [31:0] ReadLineSetsF [`ICACHE_BLOCKLENINBITS/16-1:0]; logic [31:0] ReadLineSetsF [LINELEN/16-1:0];
logic [NUMWAYS-1:0] SRAMWayWriteEnable; logic [NUMWAYS-1:0] SRAMWayWriteEnable;
@ -98,13 +97,13 @@ module icache
.y(RAdr)); .y(RAdr));
cacheway #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN), cacheway #(.NUMLINES(NUMLINES), .LINELEN(LINELEN), .TAGLEN(TAGLEN),
.OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN), .DIRTY_BITS(0)) .OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN), .DIRTY_BITS(0))
MemWay[NUMWAYS-1:0](.clk, .reset, .RAdr, MemWay[NUMWAYS-1:0](.clk, .reset, .RAdr,
.PAdr(PCPF), .PAdr(PCPF),
.WriteEnable(SRAMWayWriteEnable), .WriteEnable(SRAMWayWriteEnable),
.VDWriteEnable(1'b0), .VDWriteEnable(1'b0),
.WriteWordEnable({{(BLOCKLEN/`XLEN){1'b1}}}), .WriteWordEnable({{(LINELEN/`XLEN){1'b1}}}),
.TagWriteEnable(SRAMWayWriteEnable), .TagWriteEnable(SRAMWayWriteEnable),
.WriteData(ICacheMemWriteData), .WriteData(ICacheMemWriteData),
.SetValid(ICacheMemWriteEnable), .SetValid(ICacheMemWriteEnable),
@ -115,7 +114,6 @@ module icache
.VictimDirtyWay(), .VictimTagWay(), .VictimDirtyWay(), .VictimTagWay(),
.InvalidateAll(InvalidateICacheM)); .InvalidateAll(InvalidateICacheM));
generate
if(NUMWAYS > 1) begin:vict if(NUMWAYS > 1) begin:vict
cachereplacementpolicy #(NUMWAYS, INDEXLEN, OFFSETLEN, NUMLINES) cachereplacementpolicy #(NUMWAYS, INDEXLEN, OFFSETLEN, NUMLINES)
cachereplacementpolicy(.clk, .reset, cachereplacementpolicy(.clk, .reset,
@ -127,24 +125,20 @@ module icache
end else begin:vict end else begin:vict
assign VictimWay = 1'b1; // one hot. assign VictimWay = 1'b1; // one hot.
end end
endgenerate
assign hit = | WayHit; assign hit = | WayHit;
// ReadDataLineWayMasked is a 2d array of cache block len by number of ways. // ReadDataLineWayMasked is a 2d array of cache line len by number of ways.
// Need to OR together each way in a bitwise manner. // Need to OR together each way in a bitwise manner.
// Final part of the AO Mux. First is the AND in the cacheway. // Final part of the AO Mux. First is the AND in the cacheway.
or_rows #(NUMWAYS, BLOCKLEN) ReadDataAOMux(.a(ReadDataLineWayMasked), .y(ReadLineF)); or_rows #(NUMWAYS, LINELEN) ReadDataAOMux(.a(ReadDataLineWayMasked), .y(ReadLineF));
genvar index; genvar index;
generate for(index = 0; index < LINELEN / 16 - 1; index++)
for(index = 0; index < BLOCKLEN / 16 - 1; index++) begin:readlinesetsmux
assign ReadLineSetsF[index] = ReadLineF[((index+1)*16)+16-1 : (index*16)]; assign ReadLineSetsF[index] = ReadLineF[((index+1)*16)+16-1 : (index*16)];
end assign ReadLineSetsF[LINELEN/16-1] = {16'b0, ReadLineF[LINELEN-1:LINELEN-16]};
assign ReadLineSetsF[BLOCKLEN/16-1] = {16'b0, ReadLineF[BLOCKLEN-1:BLOCKLEN-16]};
endgenerate
assign FinalInstrRawF = ReadLineSetsF[PCPF[$clog2(BLOCKLEN / 32) + 1 : 1]]; assign FinalInstrRawF = ReadLineSetsF[PCPF[$clog2(LINELEN / 32) + 1 : 1]];
assign ICacheBusAdr = {PCPF[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}; assign ICacheBusAdr = {PCPF[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}};

4
pipelined/src/cache/icachefsm.sv vendored
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@ -59,8 +59,8 @@ module icachefsm
STATE_MISS_FETCH_WDV, // aligned miss, issue read to AHB and wait for data. STATE_MISS_FETCH_WDV, // aligned miss, issue read to AHB and wait for data.
STATE_MISS_FETCH_DONE, // write data into SRAM/LUT STATE_MISS_FETCH_DONE, // write data into SRAM/LUT
STATE_MISS_READ, // read block 1 from SRAM/LUT STATE_MISS_READ, // read line 1 from SRAM/LUT
STATE_MISS_READ_DELAY, // read block 1 from SRAM/LUT STATE_MISS_READ_DELAY, // read line 1 from SRAM/LUT
STATE_CPU_BUSY STATE_CPU_BUSY
} statetype; } statetype;

3
pipelined/src/ebu/amoalu.sv
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@ -56,7 +56,6 @@ module amoalu (
endcase endcase
// sign extend if necessary // sign extend if necessary
generate
if (`XLEN == 32) begin:sext if (`XLEN == 32) begin:sext
assign a = srca; assign a = srca;
assign b = srcb; assign b = srcb;
@ -74,7 +73,5 @@ module amoalu (
result = y; result = y;
end end
end end
endgenerate
endmodule endmodule

4
pipelined/src/fpu/cvtfp.sv
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@ -157,7 +157,7 @@ module cvtfp (
// Result Selection // Result Selection
/////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////
generate if(`IEEE754) begin if(`IEEE754) begin
// select the double to single precision result // select the double to single precision result
assign DSRes = XNaNE ? {XSgnE, {8{1'b1}}, 1'b1, XManE[50:29]} : assign DSRes = XNaNE ? {XSgnE, {8{1'b1}}, 1'b1, XManE[50:29]} :
Underflow & ~Denorm ? {XSgnE, 30'b0, CalcPlus1&(|FrmE[1:0]|Shift)} : Underflow & ~Denorm ? {XSgnE, 30'b0, CalcPlus1&(|FrmE[1:0]|Shift)} :
@ -178,8 +178,6 @@ module cvtfp (
// select the final result based on the opperation // select the final result based on the opperation
assign CvtFpResE = FmtE ? {{32{1'b1}},DSRes} : {XSgnE&~XNaNE, SDExp, SDFrac[51]|XNaNE, SDFrac[50:0]&{51{~XNaNE}}}; assign CvtFpResE = FmtE ? {{32{1'b1}},DSRes} : {XSgnE&~XNaNE, SDExp, SDFrac[51]|XNaNE, SDFrac[50:0]&{51{~XNaNE}}};
end end
endgenerate
endmodule // fpadd endmodule // fpadd

17
pipelined/src/fpu/divconv_pipe.sv
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@ -174,3 +174,20 @@ module divconv_pipe (q1, qm1, qp1, q0, qm0, qp0, rega_out, regb_out, regc_out, r
flopenr #(60) regk (clk, reset, regs_pipe2, {qp_out0[59:35], (qp_out0[34:6] & {29{~P_pipe}}), 6'h0}, qp0); flopenr #(60) regk (clk, reset, regs_pipe2, {qp_out0[59:35], (qp_out0[34:6] & {29{~P_pipe}}), 6'h0}, qp0);
endmodule // divconv endmodule // divconv
// *** rewrote behaviorally dh 5 Jan 2021 for speed
module csa #(parameter WIDTH=8) (
input logic [WIDTH-1:0] a, b, c,
output logic [WIDTH-1:0] sum, carry);
assign sum = a ^ b ^ c;
assign carry = (a & (b | c)) | (b & c);
/*
logic [WIDTH:0] carry_temp;
genvar i;
for (i=0;i<WIDTH;i=i+1) begin : genbit
fa fa_inst (a[i], b[i], c[i], sum[i], carry_temp[i+1]);
end
assign carry = {carry_temp[WIDTH-1:1], 1'b0};
*/
endmodule // csa

3
pipelined/src/fpu/fcmp.sv
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@ -71,14 +71,13 @@ module fcmp (
// - return 0 if comparison with NaN (unordered) // - return 0 if comparison with NaN (unordered)
logic [`FLEN-1:0] QNaNX, QNaNY; logic [`FLEN-1:0] QNaNX, QNaNY;
generate if(`IEEE754) begin if(`IEEE754) begin
assign QNaNX = FmtE ? {XSgnE, XExpE, 1'b1, XManE[`NF-2:0]} : {{32{1'b1}}, XSgnE, XExpE[7:0], 1'b1, XManE[50:29]}; assign QNaNX = FmtE ? {XSgnE, XExpE, 1'b1, XManE[`NF-2:0]} : {{32{1'b1}}, XSgnE, XExpE[7:0], 1'b1, XManE[50:29]};
assign QNaNY = FmtE ? {YSgnE, YExpE, 1'b1, YManE[`NF-2:0]} : {{32{1'b1}}, YSgnE, YExpE[7:0], 1'b1, YManE[50:29]}; assign QNaNY = FmtE ? {YSgnE, YExpE, 1'b1, YManE[`NF-2:0]} : {{32{1'b1}}, YSgnE, YExpE[7:0], 1'b1, YManE[50:29]};
end else begin end else begin
assign QNaNX = FmtE ? {1'b0, XExpE, 1'b1, 51'b0} : {{32{1'b1}}, 1'b0, XExpE[7:0], 1'b1, 22'b0}; assign QNaNX = FmtE ? {1'b0, XExpE, 1'b1, 51'b0} : {{32{1'b1}}, 1'b0, XExpE[7:0], 1'b1, 22'b0};
assign QNaNY = FmtE ? {1'b0, YExpE, 1'b1, 51'b0} : {{32{1'b1}}, 1'b0, YExpE[7:0], 1'b1, 22'b0}; assign QNaNY = FmtE ? {1'b0, YExpE, 1'b1, 51'b0} : {{32{1'b1}}, 1'b0, YExpE[7:0], 1'b1, 22'b0};
end end
endgenerate
always_comb begin always_comb begin
case (FOpCtrlE[2:0]) case (FOpCtrlE[2:0])

6
pipelined/src/fpu/fcvt.sv
View File

@ -173,7 +173,7 @@ module fcvt (
// - only set invalid flag for out-of-range vales // - only set invalid flag for out-of-range vales
// - set inexact if in representable range and not exact // - set inexact if in representable range and not exact
generate if(`IEEE754) begin // checks before rounding if(`IEEE754) begin // checks before rounding
assign Invalid = (Of | Uf)&FOpCtrlE[0]; assign Invalid = (Of | Uf)&FOpCtrlE[0];
assign Inexact = (Guard|Round|Sticky)&~(&FOpCtrlE[1:0]&(XSgnE|Of))&~((Of|Uf)&~FOpCtrlE[1]&FOpCtrlE[0]); assign Inexact = (Guard|Round|Sticky)&~(&FOpCtrlE[1:0]&(XSgnE|Of))&~((Of|Uf)&~FOpCtrlE[1]&FOpCtrlE[0]);
assign CvtFlgE = {Invalid&~Inexact, 3'b0, Inexact}; assign CvtFlgE = {Invalid&~Inexact, 3'b0, Inexact};
@ -182,10 +182,6 @@ module fcvt (
assign Inexact = (Guard|Round|Sticky)&~(&FOpCtrlE[1:0]&((XSgnE&~(ShiftCnt[12]&~Plus1))|Of))&~((Of|Uf)&~FOpCtrlE[1]&FOpCtrlE[0]); assign Inexact = (Guard|Round|Sticky)&~(&FOpCtrlE[1:0]&((XSgnE&~(ShiftCnt[12]&~Plus1))|Of))&~((Of|Uf)&~FOpCtrlE[1]&FOpCtrlE[0]);
assign CvtFlgE = {Invalid&~Inexact, 3'b0, Inexact}; assign CvtFlgE = {Invalid&~Inexact, 3'b0, Inexact};
end end
endgenerate
endmodule // fpadd endmodule // fpadd

7
pipelined/src/fpu/fma.sv
View File

@ -814,20 +814,17 @@ module resultselect(
); );
logic [`FLEN-1:0] XNaNResult, YNaNResult, ZNaNResult, InvalidResult, OverflowResult, KillProdResult, UnderflowResult; // possible results logic [`FLEN-1:0] XNaNResult, YNaNResult, ZNaNResult, InvalidResult, OverflowResult, KillProdResult, UnderflowResult; // possible results
generate if(`IEEE754) begin
if(`IEEE754) begin:nan
assign XNaNResult = FmtM ? {XSgnM, XExpM, 1'b1, XManM[`NF-2:0]} : {{32{1'b1}}, XSgnM, XExpM[7:0], 1'b1, XManM[50:29]}; assign XNaNResult = FmtM ? {XSgnM, XExpM, 1'b1, XManM[`NF-2:0]} : {{32{1'b1}}, XSgnM, XExpM[7:0], 1'b1, XManM[50:29]};
assign YNaNResult = FmtM ? {YSgnM, YExpM, 1'b1, YManM[`NF-2:0]} : {{32{1'b1}}, YSgnM, YExpM[7:0], 1'b1, YManM[50:29]}; assign YNaNResult = FmtM ? {YSgnM, YExpM, 1'b1, YManM[`NF-2:0]} : {{32{1'b1}}, YSgnM, YExpM[7:0], 1'b1, YManM[50:29]};
assign ZNaNResult = FmtM ? {ZSgnEffM, ZExpM, 1'b1, ZManM[`NF-2:0]} : {{32{1'b1}}, ZSgnEffM, ZExpM[7:0], 1'b1, ZManM[50:29]}; assign ZNaNResult = FmtM ? {ZSgnEffM, ZExpM, 1'b1, ZManM[`NF-2:0]} : {{32{1'b1}}, ZSgnEffM, ZExpM[7:0], 1'b1, ZManM[50:29]};
assign InvalidResult = FmtM ? {ResultSgn, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{32{1'b1}}, ResultSgn, 8'hff, 1'b1, 22'b0}; assign InvalidResult = FmtM ? {ResultSgn, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{32{1'b1}}, ResultSgn, 8'hff, 1'b1, 22'b0};
end else begin:nan end else begin
assign XNaNResult = FmtM ? {1'b0, XExpM, 1'b1, 51'b0} : {{32{1'b1}}, 1'b0, XExpM[7:0], 1'b1, 22'b0}; assign XNaNResult = FmtM ? {1'b0, XExpM, 1'b1, 51'b0} : {{32{1'b1}}, 1'b0, XExpM[7:0], 1'b1, 22'b0};
assign YNaNResult = FmtM ? {1'b0, YExpM, 1'b1, 51'b0} : {{32{1'b1}}, 1'b0, YExpM[7:0], 1'b1, 22'b0}; assign YNaNResult = FmtM ? {1'b0, YExpM, 1'b1, 51'b0} : {{32{1'b1}}, 1'b0, YExpM[7:0], 1'b1, 22'b0};
assign ZNaNResult = FmtM ? {1'b0, ZExpM, 1'b1, 51'b0} : {{32{1'b1}}, 1'b0, ZExpM[7:0], 1'b1, 22'b0}; assign ZNaNResult = FmtM ? {1'b0, ZExpM, 1'b1, 51'b0} : {{32{1'b1}}, 1'b0, ZExpM[7:0], 1'b1, 22'b0};
assign InvalidResult = FmtM ? {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{32{1'b1}}, 1'b0, 8'hff, 1'b1, 22'b0}; assign InvalidResult = FmtM ? {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{32{1'b1}}, 1'b0, 8'hff, 1'b1, 22'b0};
end end
endgenerate
assign OverflowResult = FmtM ? ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {ResultSgn, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}} : assign OverflowResult = FmtM ? ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {ResultSgn, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}} :
{ResultSgn, {`NE{1'b1}}, {`NF{1'b0}}} : {ResultSgn, {`NE{1'b1}}, {`NF{1'b0}}} :

5
pipelined/src/muldiv/redundantmul.sv → pipelined/src/fpu/redundantmul.sv
View File

@ -37,9 +37,6 @@ module redundantmul #(parameter WIDTH =8)(
input logic [WIDTH-1:0] a,b, input logic [WIDTH-1:0] a,b,
output logic [2*WIDTH-1:0] out0, out1); output logic [2*WIDTH-1:0] out0, out1);
//
generate
if (`DESIGN_COMPILER == 1) begin:mul if (`DESIGN_COMPILER == 1) begin:mul
logic [2*WIDTH-1+2:0] tmp_out0; logic [2*WIDTH-1+2:0] tmp_out0;
logic [2*WIDTH-1+2:0] tmp_out1; logic [2*WIDTH-1+2:0] tmp_out1;
@ -51,8 +48,6 @@ module redundantmul #(parameter WIDTH =8)(
assign out0 = a * b; assign out0 = a * b;
assign out1 = 0; assign out1 = 0;
end end
endgenerate
endmodule endmodule

195
pipelined/src/generic/lzd.sv
View File

@ -1,195 +0,0 @@
///////////////////////////////////////////
// lzd.sv
//
// Written: James.Stine@okstate.edu 1 February 2021
// Modified:
//
// Purpose: Integer Divide instructions
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-config.vh"
/* verilator lint_off DECLFILENAME */
// Original idea came from V. G. Oklobdzija, "An algorithmic and novel
// design of a leading zero detector circuit: comparison with logic
// synthesis," in IEEE Transactions on Very Large Scale Integration
// (VLSI) Systems, vol. 2, no. 1, pp. 124-128, March 1994, doi:
// 10.1109/92.273153.
// Modified to be more hierarchical
module lzd2 (P, V, B);
input logic [1:0] B;
output logic P;
output logic V;
assign V = B[0] | B[1];
assign P = B[0] & ~B[1];
endmodule // lzd2
module lzd_hier #(parameter WIDTH=8)
(input logic [WIDTH-1:0] B,
output logic [$clog2(WIDTH)-1:0] ZP,
output logic ZV);
if (WIDTH == 128)
lzd128 lz127 (ZP, ZV, B);
else if (WIDTH == 64)
lzd64 lz64 (ZP, ZV, B);
else if (WIDTH == 32)
lzd32 lz32 (ZP, ZV, B);
else if (WIDTH == 16)
lzd16 lz16 (ZP, ZV, B);
else if (WIDTH == 8)
lzd8 lz8 (ZP, ZV, B);
else if (WIDTH == 4)
lzd4 lz4 (ZP, ZV, B);
endmodule // lzd_hier
module lzd4 (ZP, ZV, B);
input logic [3:0] B;
logic ZPa;
logic ZPb;
logic ZVa;
logic ZVb;
output logic [1:0] ZP;
output logic ZV;
lzd2 l1(ZPa, ZVa, B[1:0]);
lzd2 l2(ZPb, ZVb, B[3:2]);
assign ZP[0] = ZVb ? ZPb : ZPa;
assign ZP[1] = ~ZVb;
assign ZV = ZVa | ZVb;
endmodule // lzd4
module lzd8 (ZP, ZV, B);
input logic [7:0] B;
logic [1:0] ZPa;
logic [1:0] ZPb;
logic ZVa;
logic ZVb;
output logic [2:0] ZP;
output logic ZV;
lzd4 l1(ZPa, ZVa, B[3:0]);
lzd4 l2(ZPb, ZVb, B[7:4]);
assign ZP[1:0] = ZVb ? ZPb : ZPa;
assign ZP[2] = ~ZVb;
assign ZV = ZVa | ZVb;
endmodule // lzd8
module lzd16 (ZP, ZV, B);
input logic [15:0] B;
logic [2:0] ZPa;
logic [2:0] ZPb;
logic ZVa;
logic ZVb;
output logic [3:0] ZP;
output logic ZV;
lzd8 l1(ZPa, ZVa, B[7:0]);
lzd8 l2(ZPb, ZVb, B[15:8]);
assign ZP[2:0] = ZVb ? ZPb : ZPa;
assign ZP[3] = ~ZVb;
assign ZV = ZVa | ZVb;
endmodule // lzd16
module lzd32 (ZP, ZV, B);
input logic [31:0] B;
logic [3:0] ZPa;
logic [3:0] ZPb;
logic ZVa;
logic ZVb;
output logic [4:0] ZP;
output logic ZV;
lzd16 l1(ZPa, ZVa, B[15:0]);
lzd16 l2(ZPb, ZVb, B[31:16]);
assign ZP[3:0] = ZVb ? ZPb : ZPa;
assign ZP[4] = ~ZVb;
assign ZV = ZVa | ZVb;
endmodule // lzd32
module lzd64 (ZP, ZV, B);
input logic [63:0] B;
logic [4:0] ZPa;
logic [4:0] ZPb;
logic ZVa;
logic ZVb;
output logic [5:0] ZP;
output logic ZV;
lzd32 l1(ZPa, ZVa, B[31:0]);
lzd32 l2(ZPb, ZVb, B[63:32]);
assign ZP[4:0] = ZVb ? ZPb : ZPa;
assign ZP[5] = ~ZVb;
assign ZV = ZVa | ZVb;
endmodule // lzd64
module lzd128 (ZP, ZV, B);
input logic [127:0] B;
logic [5:0] ZPa;
logic [5:0] ZPb;
logic ZVa;
logic ZVb;
output logic [6:0] ZP;
output logic ZV;
lzd64 l1(ZPa, ZVa, B[64:0]);
lzd64 l2(ZPb, ZVb, B[127:63]);
assign ZP[5:0] = ZVb ? ZPb : ZPa;
assign ZP[6] = ~ZVb;
assign ZV = ZVa | ZVb;
endmodule // lzd128
/* verilator lint_on DECLFILENAME */

6
pipelined/src/generic/or_rows.sv
View File

@ -33,18 +33,16 @@ module or_rows #(parameter ROWS = 8, COLS=2) (
input var logic [COLS-1:0] a[ROWS-1:0], input var logic [COLS-1:0] a[ROWS-1:0],
output logic [COLS-1:0] y); output logic [COLS-1:0] y);
logic [COLS-1:0] mid[ROWS-1:1]; genvar row;
genvar row, col;
generate
if(ROWS == 1) if(ROWS == 1)
assign y = a[0]; assign y = a[0];
else begin else begin
logic [COLS-1:0] mid[ROWS-1:1];
assign mid[1] = a[0] | a[1]; assign mid[1] = a[0] | a[1];
for (row=2; row < ROWS; row++) for (row=2; row < ROWS; row++)
assign mid[row] = mid[row-1] | a[row]; assign mid[row] = mid[row-1] | a[row];
assign y = mid[ROWS-1]; assign y = mid[ROWS-1];
end end
endgenerate
endmodule endmodule
/* verilator lint_on UNOPTFLAT */ /* verilator lint_on UNOPTFLAT */

74
pipelined/src/generic/shift.sv
View File

@ -1,74 +0,0 @@
///////////////////////////////////////////
// shifters.sv
//
// Written: James.Stine@okstate.edu 1 February 2021
// Modified:
//
// Purpose: Integer Divide instructions
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-config.vh"
/* verilator lint_off DECLFILENAME */
/* verilator lint_off UNOPTFLAT */
module shift_right #(parameter WIDTH=8)
(input logic [WIDTH-1:0] A,
input logic [$clog2(WIDTH)-1:0] Shift,
output logic [WIDTH-1:0] Z);
logic [WIDTH-1:0] stage [$clog2(WIDTH):0];
logic sign;
genvar i;
assign stage[0] = A;
generate
for (i=0;i<$clog2(WIDTH);i=i+1) begin : genbit
mux2 #(WIDTH) mux_inst (stage[i],
{{(WIDTH/(2**(i+1))){1'b0}}, stage[i][WIDTH-1:WIDTH/(2**(i+1))]},
Shift[$clog2(WIDTH)-i-1],
stage[i+1]);
end
endgenerate
assign Z = stage[$clog2(WIDTH)];
endmodule // shift_right
module shift_left #(parameter WIDTH=8)
(input logic [WIDTH-1:0] A,
input logic [$clog2(WIDTH)-1:0] Shift,
output logic [WIDTH-1:0] Z);
logic [WIDTH-1:0] stage [$clog2(WIDTH):0];
genvar i;
assign stage[0] = A;
generate
for (i=0;i<$clog2(WIDTH);i=i+1) begin : genbit
mux2 #(WIDTH) mux_inst (stage[i],
{stage[i][WIDTH-1-WIDTH/(2**(i+1)):0], {(WIDTH/(2**(i+1))){1'b0}}},
Shift[$clog2(WIDTH)-i-1],
stage[i+1]);
end
endgenerate
assign Z = stage[$clog2(WIDTH)];
endmodule // shift_left
/* verilator lint_on DECLFILENAME */
/* verilator lint_on UNOPTFLAT */

2
pipelined/src/ieu/alu.sv
View File

@ -78,9 +78,7 @@ module alu #(parameter WIDTH=32) (
endcase endcase
// support W-type RV64I ADDW/SUBW/ADDIW/Shifts that sign-extend 32-bit result to 64 bits // support W-type RV64I ADDW/SUBW/ADDIW/Shifts that sign-extend 32-bit result to 64 bits
generate
if (WIDTH==64) assign Result = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; if (WIDTH==64) assign Result = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult;
else assign Result = FullResult; else assign Result = FullResult;
endgenerate
endmodule endmodule

4
pipelined/src/ieu/controller.sv
View File

@ -109,7 +109,6 @@ module controller(
assign Rs1D = InstrD[19:15]; assign Rs1D = InstrD[19:15];
// Main Instruction Decoder // Main Instruction Decoder
generate
always_comb always_comb
case(OpD) case(OpD)
// RegWrite_ImmSrc_ALUSrc_MemRW_ResultSrc_Branch_ALUOp_Jump_ALUResultSrc_W64_CSRRead_Privileged_Fence_MulDiv_Atomic_Illegal // RegWrite_ImmSrc_ALUSrc_MemRW_ResultSrc_Branch_ALUOp_Jump_ALUResultSrc_W64_CSRRead_Privileged_Fence_MulDiv_Atomic_Illegal
@ -157,7 +156,6 @@ module controller(
ControlsD = `CTRLW'b1_000_00_00_010_0_0_0_0_0_1_0_0_0_00_0; // csrs ControlsD = `CTRLW'b1_000_00_00_010_0_0_0_0_0_1_0_0_0_00_0; // csrs
default: ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // non-implemented instruction default: ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // non-implemented instruction
endcase endcase
endgenerate
// unswizzle control bits // unswizzle control bits
// squash control signals if coming from an illegal compressed instruction // squash control signals if coming from an illegal compressed instruction
@ -181,7 +179,6 @@ module controller(
// Fences // Fences
// Ordinary fence is presently a nop // Ordinary fence is presently a nop
// FENCE.I flushes the D$ and invalidates the I$ if Zifencei is supported and I$ is implemented // FENCE.I flushes the D$ and invalidates the I$ if Zifencei is supported and I$ is implemented
generate
if (`ZIFENCEI_SUPPORTED & `MEM_ICACHE) begin:fencei if (`ZIFENCEI_SUPPORTED & `MEM_ICACHE) begin:fencei
logic FenceID; logic FenceID;
assign FenceID = FenceD & (Funct3D == 3'b001); // is it a FENCE.I instruction? assign FenceID = FenceD & (Funct3D == 3'b001); // is it a FENCE.I instruction?
@ -191,7 +188,6 @@ module controller(
assign InvalidateICacheD = 0; assign InvalidateICacheD = 0;
assign FlushDCacheD = 0; assign FlushDCacheD = 0;
end end
endgenerate
// Decocde stage pipeline control register // Decocde stage pipeline control register
flopenrc #(1) controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD); flopenrc #(1) controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD);

4
pipelined/src/ieu/datapath.sv
View File

@ -124,7 +124,6 @@ module datapath (
mux5 #(`XLEN) resultmuxW(ResultW, ReadDataW, CSRReadValW, MulDivResultW, SCResultW, ResultSrcW, WriteDataW); mux5 #(`XLEN) resultmuxW(ResultW, ReadDataW, CSRReadValW, MulDivResultW, SCResultW, ResultSrcW, WriteDataW);
// floating point interactions: fcvt, fp stores // floating point interactions: fcvt, fp stores
generate
if (`F_SUPPORTED) begin:fpmux if (`F_SUPPORTED) begin:fpmux
mux2 #(`XLEN) resultmuxM(IEUResultM, FIntResM, FWriteIntM, ResultM); mux2 #(`XLEN) resultmuxM(IEUResultM, FIntResM, FWriteIntM, ResultM);
mux2 #(`XLEN) writedatamux(ForwardedSrcBE, FWriteDataE, ~IllegalFPUInstrE, WriteDataE); mux2 #(`XLEN) writedatamux(ForwardedSrcBE, FWriteDataE, ~IllegalFPUInstrE, WriteDataE);
@ -132,11 +131,8 @@ module datapath (
assign ResultM = IEUResultM; assign ResultM = IEUResultM;
assign WriteDataE = ForwardedSrcBE; assign WriteDataE = ForwardedSrcBE;
end end
endgenerate
// handle Store Conditional result if atomic extension supported // handle Store Conditional result if atomic extension supported
generate
if (`A_SUPPORTED) assign SCResultW = {{(`XLEN-1){1'b0}}, SquashSCW}; if (`A_SUPPORTED) assign SCResultW = {{(`XLEN-1){1'b0}}, SquashSCW};
else assign SCResultW = 0; else assign SCResultW = 0;
endgenerate
endmodule endmodule

7
pipelined/src/ieu/extend.sv
View File

@ -32,7 +32,6 @@ module extend (
localparam [`XLEN-1:0] undefined = {(`XLEN){1'bx}}; // could change to 0 after debug localparam [`XLEN-1:0] undefined = {(`XLEN){1'bx}}; // could change to 0 after debug
// generate
always_comb always_comb
case(ImmSrcD) case(ImmSrcD)
// I-type // I-type
@ -48,7 +47,9 @@ module extend (
// Store Conditional: zero offset // Store Conditional: zero offset
3'b101: if (`A_SUPPORTED) ExtImmD = 0; 3'b101: if (`A_SUPPORTED) ExtImmD = 0;
else ExtImmD = undefined; else ExtImmD = undefined;
default: ExtImmD = undefined; // undefined default: begin
ExtImmD = undefined; // undefined
$error("Invalid ImmSrcD in extend");
end
endcase endcase
// endgenerate
endmodule endmodule

2
pipelined/src/ieu/shifter.sv
View File

@ -39,7 +39,6 @@ module shifter (
// For RV64, 32 and 64-bit shifts are needed, with sign extension. // For RV64, 32 and 64-bit shifts are needed, with sign extension.
// funnel shifter input (see CMOS VLSI Design 4e Section 11.8.1, note Table 11.11 shift types wrong) // funnel shifter input (see CMOS VLSI Design 4e Section 11.8.1, note Table 11.11 shift types wrong)
generate
if (`XLEN==32) begin:shifter // RV32 if (`XLEN==32) begin:shifter // RV32
always_comb // funnel mux always_comb // funnel mux
if (Right) if (Right)
@ -62,7 +61,6 @@ module shifter (
end end
assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32 or 64-bit shift assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32 or 64-bit shift
end end
endgenerate
// opposite offset for right shfits // opposite offset for right shfits
assign offset = Right ? amttrunc : ~amttrunc; assign offset = Right ? amttrunc : ~amttrunc;

5
pipelined/src/ifu/SRAM2P1R1W.sv
View File

@ -93,10 +93,8 @@ module SRAM2P1R1W
// read port // read port
assign RD1 = mem[RA1Q]; assign RD1 = mem[RA1Q];
genvar index;
// write port // write port
generate genvar index;
for (index = 0; index < WIDTH; index = index + 1) begin:bitwrite for (index = 0; index < WIDTH; index = index + 1) begin:bitwrite
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
if (WEN1Q & BitWEN1[index]) begin if (WEN1Q & BitWEN1[index]) begin
@ -104,7 +102,6 @@ module SRAM2P1R1W
end end
end end
end end
endgenerate
endmodule endmodule

2
pipelined/src/ifu/bpred.sv
View File

@ -70,7 +70,6 @@ module bpred
// Part 1 branch direction prediction // Part 1 branch direction prediction
generate
if (`BPTYPE == "BPTWOBIT") begin:Predictor if (`BPTYPE == "BPTWOBIT") begin:Predictor
twoBitPredictor DirPredictor(.clk(clk), twoBitPredictor DirPredictor(.clk(clk),
.reset(reset), .reset(reset),
@ -137,7 +136,6 @@ module bpred
.PCSrcE(PCSrcE), .PCSrcE(PCSrcE),
.UpdatePrediction(UpdateBPPredE)); .UpdatePrediction(UpdateBPPredE));
end end
endgenerate
// this predictor will have two pieces of data, // this predictor will have two pieces of data,

2
pipelined/src/ifu/decompress.sv
View File

@ -38,7 +38,6 @@ module decompress (
logic [1:0] op; logic [1:0] op;
// if the system handles compressed instructions, decode appropriately // if the system handles compressed instructions, decode appropriately
generate
if (!(`C_SUPPORTED)) begin:decompress // no compressed mode if (!(`C_SUPPORTED)) begin:decompress // no compressed mode
assign InstrD = InstrRawD; assign InstrD = InstrRawD;
assign IllegalCompInstrD = 0; assign IllegalCompInstrD = 0;
@ -173,6 +172,5 @@ module decompress (
endcase endcase
end end
end end
endgenerate
endmodule endmodule

63
pipelined/src/ifu/ifu.sv
View File

@ -111,12 +111,11 @@ module ifu (
logic [31:0] PostSpillInstrRawF; logic [31:0] PostSpillInstrRawF;
generate
if(`C_SUPPORTED) begin : SpillSupport if(`C_SUPPORTED) begin : SpillSupport
logic [`XLEN-1:0] PCFp2; logic [`XLEN-1:0] PCFp2;
logic Spill; logic Spill;
logic SelSpill, SpillSave; logic SelSpill, SpillSave;
logic [15:0] SpillDataBlock0; logic [15:0] SpillDataLine0;
// this exists only if there are compressed instructions. // this exists only if there are compressed instructions.
assign PCFp2 = PCF + `XLEN'b10; assign PCFp2 = PCF + `XLEN'b10;
@ -124,7 +123,7 @@ module ifu (
assign PCNextFMux = SelNextSpill ? PCFp2[11:0] : PCNextF[11:0]; assign PCNextFMux = SelNextSpill ? PCFp2[11:0] : PCNextF[11:0];
assign PCFMux = SelSpill ? PCFp2 : PCF; assign PCFMux = SelSpill ? PCFp2 : PCF;
assign Spill = &PCF[$clog2(`ICACHE_BLOCKLENINBITS/32)+1:1]; assign Spill = &PCF[$clog2(`ICACHE_LINELENINBITS/32)+1:1];
typedef enum {STATE_SPILL_READY, STATE_SPILL_SPILL} statetype; typedef enum {STATE_SPILL_READY, STATE_SPILL_SPILL} statetype;
(* mark_debug = "true" *) statetype CurrState, NextState; (* mark_debug = "true" *) statetype CurrState, NextState;
@ -154,19 +153,18 @@ module ifu (
.en(SpillSave), .en(SpillSave),
.reset(reset), .reset(reset),
.d(InstrRawF[15:0]), .d(InstrRawF[15:0]),
.q(SpillDataBlock0)); .q(SpillDataLine0));
assign PostSpillInstrRawF = Spill ? {InstrRawF[15:0], SpillDataBlock0} : InstrRawF; assign PostSpillInstrRawF = Spill ? {InstrRawF[15:0], SpillDataLine0} : InstrRawF;
assign CompressedF = PostSpillInstrRawF[1:0] != 2'b11; assign CompressedF = PostSpillInstrRawF[1:0] != 2'b11;
// end of spill support // end of spill support
end else begin : NoSpillSupport // block: SpillSupport end else begin : NoSpillSupport // line: SpillSupport
assign PCNextFMux = PCNextF[11:0]; assign PCNextFMux = PCNextF[11:0];
assign PCFMux = PCF; assign PCFMux = PCF;
assign SelNextSpill = 0; assign SelNextSpill = 0;
assign PostSpillInstrRawF = InstrRawF; assign PostSpillInstrRawF = InstrRawF;
end end
endgenerate
assign PCFExt = {2'b00, PCFMux}; assign PCFExt = {2'b00, PCFMux};
@ -220,30 +218,30 @@ module ifu (
// 2. cache // `MEM_ICACHE // 2. cache // `MEM_ICACHE
// 3. wire pass-through // 3. wire pass-through
localparam integer WORDSPERLINE = `MEM_ICACHE ? `ICACHE_BLOCKLENINBITS/`XLEN : 1; localparam integer WORDSPERLINE = `MEM_ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1;
localparam integer LOGWPL = `MEM_ICACHE ? $clog2(WORDSPERLINE) : 1; localparam integer LOGWPL = `MEM_ICACHE ? $clog2(WORDSPERLINE) : 1;
localparam integer BLOCKLEN = `MEM_ICACHE ? `ICACHE_BLOCKLENINBITS : `XLEN; localparam integer LINELEN = `MEM_ICACHE ? `ICACHE_LINELENINBITS : `XLEN;
localparam integer WordCountThreshold = `MEM_ICACHE ? WORDSPERLINE - 1 : 0; localparam integer WordCountThreshold = `MEM_ICACHE ? WORDSPERLINE - 1 : 0;
localparam integer BLOCKBYTELEN = BLOCKLEN/8; localparam integer LINEBYTELEN = LINELEN/8;
localparam integer OFFSETLEN = $clog2(BLOCKBYTELEN); localparam integer OFFSETLEN = $clog2(LINEBYTELEN);
logic [LOGWPL-1:0] WordCount; logic [LOGWPL-1:0] WordCount;
logic [BLOCKLEN-1:0] ICacheMemWriteData; logic [LINELEN-1:0] ICacheMemWriteData;
logic ICacheBusAck; logic ICacheBusAck;
logic [`PA_BITS-1:0] LocalIfuBusAdr; logic [`PA_BITS-1:0] LocalIfuBusAdr;
logic [`PA_BITS-1:0] ICacheBusAdr; logic [`PA_BITS-1:0] ICacheBusAdr;
logic SelUncachedAdr; logic SelUncachedAdr;
generate
if(`MEM_ICACHE) begin : icache if(`MEM_ICACHE) begin : icache
logic [1:0] IfuRWF; logic [1:0] IfuRWF;
assign IfuRWF = CacheableF ? 2'b10 : 2'b00; assign IfuRWF = CacheableF ? 2'b10 : 2'b00;
icache icache(.clk, .reset, .CPUBusy, .IgnoreRequest, .ICacheMemWriteData , .ICacheBusAck, /* -----\/----- EXCLUDED -----\/-----
icache #(.LINELEN(`ICACHE_LINELENINBITS),
.NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
.NUMWAYS(`ICACHE_NUMWAYS))
icache(.clk, .reset, .CPUBusy, .IgnoreRequest, .ICacheMemWriteData , .ICacheBusAck,
.ICacheBusAdr, .ICacheStallF, .FinalInstrRawF, .ICacheBusAdr, .ICacheStallF, .FinalInstrRawF,
.ICacheFetchLine, .ICacheFetchLine,
.IfuRWF(IfuRWF), //aways read .IfuRWF(IfuRWF), //aways read
@ -251,15 +249,38 @@ module ifu (
.PCPF(PCPF), .PCPF(PCPF),
.PCF(PCFMux), .PCF(PCFMux),
.InvalidateICacheM); .InvalidateICacheM);
-----/\----- EXCLUDED -----/\----- */
end else begin : passthrough logic [`XLEN-1:0] FinalInstrRawF_FIXME;
cache #(.LINELEN(`ICACHE_LINELENINBITS),
.NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
.NUMWAYS(`ICACHE_NUMWAYS), .DCACHE(0))
icache(.clk, .reset, .CPUBusy, .IgnoreRequest, .CacheMemWriteData(ICacheMemWriteData) , .CacheBusAck(ICacheBusAck),
.CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), .ReadDataWord(FinalInstrRawF_FIXME),
.CacheFetchLine(ICacheFetchLine),
.CacheWriteLine(),
.ReadDataLineSets(),
.CacheMiss(),
.CacheAccess(),
.FinalWriteData('0),
.RW(IfuRWF), //aways read
.Atomic(2'b00),
.FlushCache(1'b0),
.LsuAdrE(PCNextFMux), // fixme
.LsuPAdrM(PCPF), // fixme
.PreLsuPAdrM(PCFMux[11:0]), //fixme
.CacheCommitted(),
.InvalidateCacheM(InvalidateICacheM));
assign FinalInstrRawF = FinalInstrRawF_FIXME[31:0];
end else begin
assign ICacheFetchLine = 0; assign ICacheFetchLine = 0;
assign ICacheBusAdr = 0; assign ICacheBusAdr = 0;
//assign CompressedF = 0; //? //assign CompressedF = 0; //?
assign ICacheStallF = 0; assign ICacheStallF = 0;
assign FinalInstrRawF = 0; assign FinalInstrRawF = 0;
end end
endgenerate
// select between dcache and direct from the BUS. Always selected if no dcache. // select between dcache and direct from the BUS. Always selected if no dcache.
// handled in the busfsm. // handled in the busfsm.
@ -270,14 +291,12 @@ module ifu (
// always present // always present
genvar index; genvar index;
generate
for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer
flopen #(`XLEN) fb(.clk(clk), flopen #(`XLEN) fb(.clk(clk),
.en(IfuBusAck & IfuBusRead & (index == WordCount)), .en(IfuBusAck & IfuBusRead & (index == WordCount)),
.d(IfuBusHRDATA), .d(IfuBusHRDATA),
.q(ICacheMemWriteData[(index+1)*`XLEN-1:index*`XLEN])); .q(ICacheMemWriteData[(index+1)*`XLEN-1:index*`XLEN]));
end end
endgenerate
assign LocalIfuBusAdr = SelUncachedAdr ? PCPF : ICacheBusAdr; assign LocalIfuBusAdr = SelUncachedAdr ? PCPF : ICacheBusAdr;
assign IfuBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalIfuBusAdr; assign IfuBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalIfuBusAdr;
@ -351,7 +370,6 @@ module ifu (
flopenl #(`XLEN) pcreg(clk, reset, ~StallF & ~ICacheStallF, PCNextF, `RESET_VECTOR, PCF); flopenl #(`XLEN) pcreg(clk, reset, ~StallF & ~ICacheStallF, PCNextF, `RESET_VECTOR, PCF);
// branch and jump predictor // branch and jump predictor
generate
if (`BPRED_ENABLED == 1) begin : bpred if (`BPRED_ENABLED == 1) begin : bpred
bpred bpred(.clk, .reset, bpred bpred(.clk, .reset,
.StallF, .StallD, .StallE, .StallF, .StallD, .StallE,
@ -369,7 +387,6 @@ module ifu (
assign RASPredPCWrongE = 1'b0; assign RASPredPCWrongE = 1'b0;
assign BPPredClassNonCFIWrongE = 1'b0; assign BPPredClassNonCFIWrongE = 1'b0;
end end
endgenerate
// The true correct target is IEUAdrE if PCSrcE is 1 else it is the fall through PCLinkE. // The true correct target is IEUAdrE if PCSrcE is 1 else it is the fall through PCLinkE.
assign PCCorrectE = PCSrcE ? IEUAdrE : PCLinkE; assign PCCorrectE = PCSrcE ? IEUAdrE : PCLinkE;

10
pipelined/src/ifu/localHistoryPredictor.sv
View File

@ -66,16 +66,10 @@ module localHistoryPredictor
// .BitWEN1(2'b11)); // .BitWEN1(2'b11));
genvar index; genvar index;
generate
for (index = 0; index < 2**m; index = index +1) begin:localhist for (index = 0; index < 2**m; index = index +1) begin:localhist
flopenr #(k) LocalHistoryRegister(.clk, .reset, .en(UpdateEN & (index == UpdatePCIndex)),
flopenr #(k) LocalHistoryRegister(.clk(clk), .d(LHRFNext), .q(LHRNextF[index]));
.reset(reset),
.en(UpdateEN & (index == UpdatePCIndex)),
.d(LHRFNext),
.q(LHRNextF[index]));
end end
endgenerate
// need to forward when updating to the same address as reading. // need to forward when updating to the same address as reading.
// first we compare to see if the update and lookup addreses are the same // first we compare to see if the update and lookup addreses are the same

51
pipelined/src/lsu/lsu.sv
View File

@ -120,7 +120,6 @@ module lsu
flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM); flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
assign IEUAdrExtM = {2'b00, IEUAdrM}; assign IEUAdrExtM = {2'b00, IEUAdrM};
generate
if(`MEM_VIRTMEM) begin : MEM_VIRTMEM if(`MEM_VIRTMEM) begin : MEM_VIRTMEM
logic AnyCPUReqM; logic AnyCPUReqM;
logic [`PA_BITS-1:0] HPTWAdr; logic [`PA_BITS-1:0] HPTWAdr;
@ -188,7 +187,6 @@ module lsu
assign DTLBLoadPageFaultM = 1'b0; assign DTLBLoadPageFaultM = 1'b0;
assign DTLBStorePageFaultM = 1'b0; assign DTLBStorePageFaultM = 1'b0;
end end
endgenerate
// **** look into this confusing signal. // **** look into this confusing signal.
// This signal is confusing. CommittedM tells the CPU's trap unit the current instruction // This signal is confusing. CommittedM tells the CPU's trap unit the current instruction
@ -200,7 +198,6 @@ module lsu
// to flush the memory operation at that time. // to flush the memory operation at that time.
assign CommittedM = SelHPTW | DCacheCommittedM | BusCommittedM; assign CommittedM = SelHPTW | DCacheCommittedM | BusCommittedM;
generate
if(`ZICSR_SUPPORTED == 1) begin : dmmu if(`ZICSR_SUPPORTED == 1) begin : dmmu
logic DataMisalignedM; logic DataMisalignedM;
@ -249,14 +246,10 @@ module lsu
assign LoadMisalignedFaultM = 0; assign LoadMisalignedFaultM = 0;
assign StoreMisalignedFaultM = 0; assign StoreMisalignedFaultM = 0;
end end
endgenerate
assign LSUStall = DCacheStall | InterlockStall | BusStall; assign LSUStall = DCacheStall | InterlockStall | BusStall;
// Move generate from lrsc to outside this module.
// use PreLsu as prefix for lrsc // use PreLsu as prefix for lrsc
generate
if (`A_SUPPORTED) begin:lrsc if (`A_SUPPORTED) begin:lrsc
assign MemReadM = PreLsuRWM[1] & ~(IgnoreRequest) & ~DTLBMissM; assign MemReadM = PreLsuRWM[1] & ~(IgnoreRequest) & ~DTLBMissM;
lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .PreLsuRWM, .LsuAtomicM, .LsuPAdrM, lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .PreLsuRWM, .LsuAtomicM, .LsuPAdrM,
@ -265,7 +258,6 @@ module lsu
assign SquashSCW = 0; assign SquashSCW = 0;
assign LsuRWM = PreLsuRWM; assign LsuRWM = PreLsuRWM;
end end
endgenerate
// conditional // conditional
@ -273,20 +265,20 @@ module lsu
// 2. cache `MEM_DCACHE // 2. cache `MEM_DCACHE
// 3. wire pass-through // 3. wire pass-through
localparam integer WORDSPERLINE = `MEM_DCACHE ? `DCACHE_BLOCKLENINBITS/`XLEN : 1; localparam integer WORDSPERLINE = `MEM_DCACHE ? `DCACHE_LINELENINBITS/`XLEN : 1;
localparam integer LOGWPL = `MEM_DCACHE ? $clog2(WORDSPERLINE) : 1; localparam integer LOGWPL = `MEM_DCACHE ? $clog2(WORDSPERLINE) : 1;
localparam integer BLOCKLEN = `MEM_DCACHE ? `DCACHE_BLOCKLENINBITS : `XLEN; localparam integer LINELEN = `MEM_DCACHE ? `DCACHE_LINELENINBITS : `XLEN;
localparam integer WordCountThreshold = `MEM_DCACHE ? WORDSPERLINE - 1 : 0; localparam integer WordCountThreshold = `MEM_DCACHE ? WORDSPERLINE - 1 : 0;
localparam integer BLOCKBYTELEN = BLOCKLEN/8; localparam integer LINEBYTELEN = LINELEN/8;
localparam integer OFFSETLEN = $clog2(BLOCKBYTELEN); localparam integer OFFSETLEN = $clog2(LINEBYTELEN);
// temp // temp
logic [`XLEN-1:0] FinalAMOWriteDataM, FinalWriteDataM; logic [`XLEN-1:0] FinalAMOWriteDataM, FinalWriteDataM;
(* mark_debug = "true" *) logic [`XLEN-1:0] PreLsuBusHWDATA; (* mark_debug = "true" *) logic [`XLEN-1:0] PreLsuBusHWDATA;
logic [`XLEN-1:0] ReadDataWordM; logic [`XLEN-1:0] ReadDataWordM;
logic [BLOCKLEN-1:0] DCacheMemWriteData; logic [LINELEN-1:0] DCacheMemWriteData;
// keep // keep
logic [`XLEN-1:0] ReadDataWordMuxM; logic [`XLEN-1:0] ReadDataWordMuxM;
@ -294,7 +286,7 @@ module lsu
logic [`PA_BITS-1:0] DCacheBusAdr; logic [`PA_BITS-1:0] DCacheBusAdr;
logic [`XLEN-1:0] ReadDataBlockSetsM [WORDSPERLINE-1:0]; logic [`XLEN-1:0] ReadDataLineSetsM [WORDSPERLINE-1:0];
@ -304,15 +296,17 @@ module lsu
logic SelUncachedAdr; logic SelUncachedAdr;
generate
if(`MEM_DCACHE) begin : dcache if(`MEM_DCACHE) begin : dcache
dcache dcache(.clk, .reset, .CPUBusy, cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
.LsuRWM, .FlushDCacheM, .LsuAtomicM, .LsuAdrE, .LsuPAdrM, .PreLsuPAdrM(PreLsuPAdrM[11:0]), // still don't like this name PreLsuPAdrM, not always physical .NUMWAYS(`DCACHE_NUMWAYS), .DCACHE(1))
.FinalWriteDataM, .ReadDataWordM, .DCacheStall, dcache(.clk, .reset, .CPUBusy,
.DCacheMiss, .DCacheAccess, .RW(CacheableM ? LsuRWM : 2'b00), .FlushCache(FlushDCacheM), .Atomic(CacheableM ? LsuAtomicM : 2'b00),
.IgnoreRequest, .CacheableM, .DCacheCommittedM, .LsuAdrE, .LsuPAdrM, .PreLsuPAdrM(PreLsuPAdrM[11:0]), // still don't like this name PreLsuPAdrM, not always physical
.DCacheBusAdr, .ReadDataBlockSetsM, .DCacheMemWriteData, .FinalWriteData(FinalWriteDataM), .ReadDataWord(ReadDataWordM), .CacheStall(DCacheStall),
.DCacheFetchLine, .DCacheWriteLine,.DCacheBusAck); .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess),
.IgnoreRequest, .CacheCommitted(DCacheCommittedM),
.CacheBusAdr(DCacheBusAdr), .ReadDataLineSets(ReadDataLineSetsM), .CacheMemWriteData(DCacheMemWriteData),
.CacheFetchLine(DCacheFetchLine), .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCacheM(1'b0));
end else begin : passthrough end else begin : passthrough
assign ReadDataWordM = 0; assign ReadDataWordM = 0;
assign DCacheStall = 0; assign DCacheStall = 0;
@ -322,9 +316,8 @@ module lsu
assign DCacheWriteLine = 0; assign DCacheWriteLine = 0;
assign DCacheFetchLine = 0; assign DCacheFetchLine = 0;
assign DCacheBusAdr = 0; assign DCacheBusAdr = 0;
assign ReadDataBlockSetsM[0] = 0; assign ReadDataLineSetsM[0] = 0;
end end
endgenerate
// select between dcache and direct from the BUS. Always selected if no dcache. // select between dcache and direct from the BUS. Always selected if no dcache.
@ -340,7 +333,6 @@ module lsu
.Funct3M(LsuFunct3M), .Funct3M(LsuFunct3M),
.ReadDataM); .ReadDataM);
generate
if (`A_SUPPORTED) begin : amo if (`A_SUPPORTED) begin : amo
logic [`XLEN-1:0] AMOResult; logic [`XLEN-1:0] AMOResult;
amoalu amoalu(.srca(ReadDataM), .srcb(WriteDataM), .funct(Funct7M), .width(LsuFunct3M[1:0]), amoalu amoalu(.srca(ReadDataM), .srcb(WriteDataM), .funct(Funct7M), .width(LsuFunct3M[1:0]),
@ -348,7 +340,6 @@ module lsu
mux2 #(`XLEN) wdmux(WriteDataM, AMOResult, LsuAtomicM[1], FinalAMOWriteDataM); mux2 #(`XLEN) wdmux(WriteDataM, AMOResult, LsuAtomicM[1], FinalAMOWriteDataM);
end else end else
assign FinalAMOWriteDataM = WriteDataM; assign FinalAMOWriteDataM = WriteDataM;
endgenerate
// this might only get instantiated if there is a dcache or dtim. // this might only get instantiated if there is a dcache or dtim.
// There is a copy in the ebu. // There is a copy in the ebu.
@ -365,24 +356,20 @@ module lsu
logic [LOGWPL-1:0] WordCount; logic [LOGWPL-1:0] WordCount;
genvar index; genvar index;
generate
for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer
flopen #(`XLEN) fb(.clk(clk), flopen #(`XLEN) fb(.clk,
.en(LsuBusAck & LsuBusRead & (index == WordCount)), .en(LsuBusAck & LsuBusRead & (index == WordCount)),
.d(LsuBusHRDATA), .d(LsuBusHRDATA),
.q(DCacheMemWriteData[(index+1)*`XLEN-1:index*`XLEN])); .q(DCacheMemWriteData[(index+1)*`XLEN-1:index*`XLEN]));
end end
endgenerate
assign LocalLsuBusAdr = SelUncachedAdr ? LsuPAdrM : DCacheBusAdr ; assign LocalLsuBusAdr = SelUncachedAdr ? LsuPAdrM : DCacheBusAdr ;
assign LsuBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalLsuBusAdr; assign LsuBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalLsuBusAdr;
assign PreLsuBusHWDATA = ReadDataBlockSetsM[WordCount]; assign PreLsuBusHWDATA = ReadDataLineSetsM[WordCount];
assign LsuBusHWDATA = SelUncachedAdr ? WriteDataM : PreLsuBusHWDATA; // *** why is this not FinalWriteDataM? which does not work. assign LsuBusHWDATA = SelUncachedAdr ? WriteDataM : PreLsuBusHWDATA; // *** why is this not FinalWriteDataM? which does not work.
generate
if (`XLEN == 32) assign LsuBusSize = SelUncachedAdr ? LsuFunct3M : 3'b010; if (`XLEN == 32) assign LsuBusSize = SelUncachedAdr ? LsuFunct3M : 3'b010;
else assign LsuBusSize = SelUncachedAdr ? LsuFunct3M : 3'b011; else assign LsuBusSize = SelUncachedAdr ? LsuFunct3M : 3'b011;
endgenerate;
busfsm #(WordCountThreshold, LOGWPL, `MEM_DCACHE) busfsm #(WordCountThreshold, LOGWPL, `MEM_DCACHE)
busfsm(.clk, .reset, .IgnoreRequest, .LsuRWM, .DCacheFetchLine, .DCacheWriteLine, busfsm(.clk, .reset, .IgnoreRequest, .LsuRWM, .DCacheFetchLine, .DCacheWriteLine,

2
pipelined/src/lsu/subwordread.sv
View File

@ -38,7 +38,6 @@ module subwordread
// Funct3M[2] is the unsigned bit. mask upper bits. // Funct3M[2] is the unsigned bit. mask upper bits.
// Funct3M[1:0] is the size of the memory access. // Funct3M[1:0] is the size of the memory access.
generate
if (`XLEN == 64) begin:swrmux if (`XLEN == 64) begin:swrmux
// ByteMe mux // ByteMe mux
always_comb always_comb
@ -110,5 +109,4 @@ module subwordread
default: ReadDataM = ReadDataWordMuxM; default: ReadDataM = ReadDataWordMuxM;
endcase endcase
end end
endgenerate
endmodule endmodule

2
pipelined/src/mmu/hptw.sv
View File

@ -52,7 +52,7 @@ module hptw
L1_ADR, L1_RD, L1_ADR, L1_RD,
L2_ADR, L2_RD, L2_ADR, L2_RD,
L3_ADR, L3_RD, L3_ADR, L3_RD,
LEAF, IDLE} statetype; // *** placed outside generate statement to remove synthesis errors LEAF, IDLE} statetype;
logic DTLBWalk; // register TLBs translation miss requests logic DTLBWalk; // register TLBs translation miss requests
logic [`PPN_BITS-1:0] BasePageTablePPN; logic [`PPN_BITS-1:0] BasePageTablePPN;

2
pipelined/src/mmu/mmu.sv
View File

@ -90,7 +90,6 @@ module mmu #(parameter TLB_ENTRIES = 8, // number of TLB Entries
// only instantiate TLB if Virtual Memory is supported // only instantiate TLB if Virtual Memory is supported
generate
if (`MEM_VIRTMEM) begin:tlb if (`MEM_VIRTMEM) begin:tlb
logic ReadAccess, WriteAccess; logic ReadAccess, WriteAccess;
assign ReadAccess = ExecuteAccessF | ReadAccessM; // execute also acts as a TLB read. Execute and Read are never active for the same MMU, so safe to mix pipestages assign ReadAccess = ExecuteAccessF | ReadAccessM; // execute also acts as a TLB read. Execute and Read are never active for the same MMU, so safe to mix pipestages
@ -110,7 +109,6 @@ module mmu #(parameter TLB_ENTRIES = 8, // number of TLB Entries
assign TLBHit = 1; // *** is this necessary assign TLBHit = 1; // *** is this necessary
assign TLBPageFault = 0; assign TLBPageFault = 0;
end end
endgenerate
// If translation is occuring, select translated physical address from TLB // If translation is occuring, select translated physical address from TLB
mux2 #(`PA_BITS) addressmux(PAdr, TLBPAdr, Translate, PhysicalAddress); mux2 #(`PA_BITS) addressmux(PAdr, TLBPAdr, Translate, PhysicalAddress);

2
pipelined/src/mmu/pmpadrdec.sv
View File

@ -68,7 +68,7 @@ module pmpadrdec (
assign NAMask[1:0] = {2'b11}; assign NAMask[1:0] = {2'b11};
assign NAMask[`PA_BITS-1:2] = (PMPAdr[`PA_BITS-3:0] + {{(`PA_BITS-3){1'b0}}, (AdrMode == NAPOT)}) ^ PMPAdr[`PA_BITS-3:0]; assign NAMask[`PA_BITS-1:2] = (PMPAdr[`PA_BITS-3:0] + {{(`PA_BITS-3){1'b0}}, (AdrMode == NAPOT)}) ^ PMPAdr[`PA_BITS-3:0];
// generates a mask where the bottom k bits are 1, corresponding to a size of 2^k bytes for this memory region. // form a mask where the bottom k bits are 1, corresponding to a size of 2^k bytes for this memory region.
// This assumes we're using at least an NA4 region, but works for any size NAPOT region. // This assumes we're using at least an NA4 region, but works for any size NAPOT region.
assign NABase = {(PMPAdr[`PA_BITS-3:0] & ~NAMask[`PA_BITS-1:2]), 2'b00}; // base physical address of the pmp. assign NABase = {(PMPAdr[`PA_BITS-3:0] & ~NAMask[`PA_BITS-1:2]), 2'b00}; // base physical address of the pmp.

3
pipelined/src/mmu/pmpchecker.sv
View File

@ -47,7 +47,6 @@ module pmpchecker (
output logic PMPStoreAccessFaultM output logic PMPStoreAccessFaultM
); );
generate
if (`PMP_ENTRIES > 0) begin: pmpchecker if (`PMP_ENTRIES > 0) begin: pmpchecker
// Bit i is high when the address falls in PMP region i // Bit i is high when the address falls in PMP region i
logic EnforcePMP; logic EnforcePMP;
@ -78,6 +77,4 @@ module pmpchecker (
assign PMPLoadAccessFaultM = 0; assign PMPLoadAccessFaultM = 0;
assign PMPStoreAccessFaultM = 0; assign PMPStoreAccessFaultM = 0;
end end
endgenerate
//assign PMPSquashBusAccess = PMPInstrAccessFaultF | PMPLoadAccessFaultM | PMPStoreAccessFaultM;
endmodule endmodule

18
pipelined/src/mmu/priorityonehot.sv
View File

@ -34,25 +34,9 @@ module priorityonehot #(parameter ENTRIES = 8) (
input logic [ENTRIES-1:0] a, input logic [ENTRIES-1:0] a,
output logic [ENTRIES-1:0] y output logic [ENTRIES-1:0] y
); );
/* verilator lint_off UNOPTFLAT */
logic [ENTRIES-1:0] nolower; logic [ENTRIES-1:0] nolower;
// generate thermometer code mask // create thermometer code mask
prioritythermometer #(ENTRIES) maskgen(.a({a[ENTRIES-2:0], 1'b1}), .y(nolower)); prioritythermometer #(ENTRIES) maskgen(.a({a[ENTRIES-2:0], 1'b1}), .y(nolower));
// genvar i;
// generate
// assign nolower[0] = 1'b1;
// for (i=1; i<ENTRIES; i++) begin:therm
// assign nolower[i] = nolower[i-1] & ~a[i-1];
// end
// endgenerate
// *** replace mask generation logic ^^^ with priority thermometer
assign y = a & nolower; assign y = a & nolower;
/* verilator lint_on UNOPTFLAT */
endmodule endmodule

11
pipelined/src/mmu/prioritythermometer.sv
View File

@ -37,20 +37,15 @@ module prioritythermometer #(parameter N = 8) (
output logic [N-1:0] y output logic [N-1:0] y
); );
// Carefully crafted so design compiler would synthesize into a fast tree structure // Carefully crafted so design compiler will synthesize into a fast tree structure
// Rather than linear. // Rather than linear.
// generate thermometer code mask // create thermometer code mask
genvar i; genvar i;
generate
assign y[0] = a[0]; assign y[0] = a[0];
for (i=1; i<N; i++) begin:therm for (i=1; i<N; i++) begin:therm
assign y[i] = y[i-1] & ~a[i]; // *** made to be the same as onehot (without the inverter) to see if the probelme is something weird with synthesis assign y[i] = y[i-1] & ~a[i];
// assign y[i] = y[i-1] & a[i];
end end
endgenerate
endmodule endmodule

2
pipelined/src/mmu/tlbcamline.sv
View File

@ -60,7 +60,6 @@ module tlbcamline #(parameter KEY_BITS = 20,
assign MatchASID = (SATP_ASID == Key_ASID) | PTE_G; assign MatchASID = (SATP_ASID == Key_ASID) | PTE_G;
generate
if (`XLEN == 32) begin: match if (`XLEN == 32) begin: match
assign {Key_ASID, Key1, Key0} = Key; assign {Key_ASID, Key1, Key0} = Key;
@ -91,7 +90,6 @@ module tlbcamline #(parameter KEY_BITS = 20,
assign Match = Match0 & Match1 & Match2 & Match3 & MatchASID & Valid; assign Match = Match0 & Match1 & Match2 & Match3 & MatchASID & Valid;
end end
endgenerate
// On a write, update the type of the page referred to by this line. // On a write, update the type of the page referred to by this line.
flopenr #(2) pagetypeflop(clk, reset, WriteEnable, PageTypeWriteVal, PageType); flopenr #(2) pagetypeflop(clk, reset, WriteEnable, PageTypeWriteVal, PageType);

12
pipelined/src/mmu/tlbcontrol.sv
View File

@ -60,14 +60,14 @@ module tlbcontrol #(parameter ITLB = 0) (
logic UpperBitsUnequalPageFault; logic UpperBitsUnequalPageFault;
logic DAPageFault; logic DAPageFault;
logic TLBAccess; logic TLBAccess;
logic ImproperPrivilege;
// Grab the sv mode from SATP and determine whether translation should occur // Grab the sv mode from SATP and determine whether translation should occur
assign EffectivePrivilegeMode = (ITLB == 1) ? PrivilegeModeW : (STATUS_MPRV ? STATUS_MPP : PrivilegeModeW); // DTLB uses MPP mode when MPRV is 1 assign EffectivePrivilegeMode = (ITLB == 1) ? PrivilegeModeW : (STATUS_MPRV ? STATUS_MPP : PrivilegeModeW); // DTLB uses MPP mode when MPRV is 1
assign Translate = (SATP_MODE != `NO_TRANSLATE) & (EffectivePrivilegeMode != `M_MODE) & ~DisableTranslation; assign Translate = (SATP_MODE != `NO_TRANSLATE) & (EffectivePrivilegeMode != `M_MODE) & ~DisableTranslation;
generate
if (`XLEN==64) begin:rv64 if (`XLEN==64) begin:rv64
assign SV39Mode = (SATP_MODE == `SV39); assign SV39Mode = (SATP_MODE == `SV39);
// generate page fault if upper bits aren't all the same // page fault if upper bits aren't all the same
logic UpperEqual39, UpperEqual48; logic UpperEqual39, UpperEqual48;
assign UpperEqual39 = &(VAdr[63:38]) | ~|(VAdr[63:38]); assign UpperEqual39 = &(VAdr[63:38]) | ~|(VAdr[63:38]);
assign UpperEqual48 = &(VAdr[63:47]) | ~|(VAdr[63:47]); assign UpperEqual48 = &(VAdr[63:47]) | ~|(VAdr[63:47]);
@ -76,23 +76,18 @@ module tlbcontrol #(parameter ITLB = 0) (
assign SV39Mode = 0; assign SV39Mode = 0;
assign UpperBitsUnequalPageFault = 0; assign UpperBitsUnequalPageFault = 0;
end end
endgenerate
// Determine whether TLB is being used // Determine whether TLB is being used
assign TLBAccess = ReadAccess | WriteAccess; assign TLBAccess = ReadAccess | WriteAccess;
// Check whether upper bits of virtual addresss are all equal // Check whether upper bits of virtual addresss are all equal
// unswizzle useful PTE bits // unswizzle useful PTE bits
assign {PTE_D, PTE_A} = PTEAccessBits[7:6]; assign {PTE_D, PTE_A} = PTEAccessBits[7:6];
assign {PTE_U, PTE_X, PTE_W, PTE_R, PTE_V} = PTEAccessBits[4:0]; assign {PTE_U, PTE_X, PTE_W, PTE_R, PTE_V} = PTEAccessBits[4:0];
// Check whether the access is allowed, page faulting if not. // Check whether the access is allowed, page faulting if not.
generate
if (ITLB == 1) begin:itlb // Instruction TLB fault checking if (ITLB == 1) begin:itlb // Instruction TLB fault checking
logic ImproperPrivilege;
// User mode may only execute user mode pages, and supervisor mode may // User mode may only execute user mode pages, and supervisor mode may
// only execute non-user mode pages. // only execute non-user mode pages.
assign ImproperPrivilege = ((EffectivePrivilegeMode == `U_MODE) & ~PTE_U) | assign ImproperPrivilege = ((EffectivePrivilegeMode == `U_MODE) & ~PTE_U) |
@ -101,7 +96,7 @@ module tlbcontrol #(parameter ITLB = 0) (
assign DAPageFault = ~PTE_A; assign DAPageFault = ~PTE_A;
assign TLBPageFault = (Translate & TLBHit & (ImproperPrivilege | ~PTE_X | DAPageFault | UpperBitsUnequalPageFault | Misaligned | ~PTE_V)); assign TLBPageFault = (Translate & TLBHit & (ImproperPrivilege | ~PTE_X | DAPageFault | UpperBitsUnequalPageFault | Misaligned | ~PTE_V));
end else begin:dtlb // Data TLB fault checking end else begin:dtlb // Data TLB fault checking
logic ImproperPrivilege, InvalidRead, InvalidWrite; logic InvalidRead, InvalidWrite;
// User mode may only load/store from user mode pages, and supervisor mode // User mode may only load/store from user mode pages, and supervisor mode
// may only access user mode pages when STATUS_SUM is low. // may only access user mode pages when STATUS_SUM is low.
@ -118,7 +113,6 @@ module tlbcontrol #(parameter ITLB = 0) (
assign DAPageFault = ~PTE_A | WriteAccess & ~PTE_D; assign DAPageFault = ~PTE_A | WriteAccess & ~PTE_D;
assign TLBPageFault = (Translate & TLBHit & (ImproperPrivilege | InvalidRead | InvalidWrite | DAPageFault | UpperBitsUnequalPageFault | Misaligned | ~PTE_V)); assign TLBPageFault = (Translate & TLBHit & (ImproperPrivilege | InvalidRead | InvalidWrite | DAPageFault | UpperBitsUnequalPageFault | Misaligned | ~PTE_V));
end end
endgenerate
assign TLBHit = CAMHit & TLBAccess; assign TLBHit = CAMHit & TLBAccess;
assign TLBMiss = (~CAMHit | TLBFlush) & Translate & TLBAccess; assign TLBMiss = (~CAMHit | TLBFlush) & Translate & TLBAccess;

2
pipelined/src/mmu/tlbmixer.sv
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@ -43,7 +43,6 @@ module tlbmixer (
logic [`PPN_BITS-1:0] PPNMixed; logic [`PPN_BITS-1:0] PPNMixed;
// produce PageNumberMask with 1s where virtual page number bits should be untranslaetd for superpages // produce PageNumberMask with 1s where virtual page number bits should be untranslaetd for superpages
generate
if (`XLEN == 32) if (`XLEN == 32)
// kilopage: 22 bits of PPN, 0 bits of VPN // kilopage: 22 bits of PPN, 0 bits of VPN
// megapage: 12 bits of PPN, 10 bits of VPN // megapage: 12 bits of PPN, 10 bits of VPN
@ -54,7 +53,6 @@ module tlbmixer (
// gigapage: 26 bits of PPN, 18 bits of VPN // gigapage: 26 bits of PPN, 18 bits of VPN
// terapage: 17 bits of PPN, 27 bits of VPN // terapage: 17 bits of PPN, 27 bits of VPN
mux4 #(44) pnm(44'h00000000000, 44'h000000001FF, 44'h0000003FFFF, 44'h00007FFFFFF, HitPageType, PageNumberMask); mux4 #(44) pnm(44'h00000000000, 44'h000000001FF, 44'h0000003FFFF, 44'h00007FFFFFF, HitPageType, PageNumberMask);
endgenerate
// merge low segments of VPN with high segments of PPN decided by the pagetype. // merge low segments of VPN with high segments of PPN decided by the pagetype.
assign ZeroExtendedVPN = {{EXTRA_BITS{1'b0}}, VPN}; // forces the VPN to be the same width as PPN. assign ZeroExtendedVPN = {{EXTRA_BITS{1'b0}}, VPN}; // forces the VPN to be the same width as PPN.

1376
pipelined/src/muldiv/div.sv
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File diff suppressed because it is too large Load Diff

4
pipelined/src/muldiv/intdivrestoring.sv
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@ -60,7 +60,6 @@ module intdivrestoring (
assign DivBusyE = (state == BUSY) | DivStartE; assign DivBusyE = (state == BUSY) | DivStartE;
// Handle sign extension for W-type instructions // Handle sign extension for W-type instructions
generate
if (`XLEN == 64) begin:rv64 // RV64 has W-type instructions if (`XLEN == 64) begin:rv64 // RV64 has W-type instructions
mux2 #(`XLEN) xinmux(ForwardedSrcAE, {ForwardedSrcAE[31:0], 32'b0}, W64E, XinE); mux2 #(`XLEN) xinmux(ForwardedSrcAE, {ForwardedSrcAE[31:0], 32'b0}, W64E, XinE);
mux2 #(`XLEN) dinmux(ForwardedSrcBE, {{32{ForwardedSrcBE[31]&DivSignedE}}, ForwardedSrcBE[31:0]}, W64E, DinE); mux2 #(`XLEN) dinmux(ForwardedSrcBE, {{32{ForwardedSrcBE[31]&DivSignedE}}, ForwardedSrcBE[31:0]}, W64E, DinE);
@ -68,7 +67,6 @@ module intdivrestoring (
assign XinE = ForwardedSrcAE; assign XinE = ForwardedSrcAE;
assign DinE = ForwardedSrcBE; assign DinE = ForwardedSrcBE;
end end
endgenerate
// Extract sign bits and check fo division by zero // Extract sign bits and check fo division by zero
assign SignDE = DivSignedE & DinE[`XLEN-1]; assign SignDE = DivSignedE & DinE[`XLEN-1];
@ -97,11 +95,9 @@ module intdivrestoring (
flopen #(3) Div0eMReg(clk, DivStartE, {Div0E, NegQE, SignXE}, {Div0M, NegQM, NegWM}); flopen #(3) Div0eMReg(clk, DivStartE, {Div0E, NegQE, SignXE}, {Div0M, NegQM, NegWM});
// one copy of divstep for each bit produced per cycle // one copy of divstep for each bit produced per cycle
generate
genvar i; genvar i;
for (i=0; i<`DIV_BITSPERCYCLE; i = i+1) for (i=0; i<`DIV_BITSPERCYCLE; i = i+1)
intdivrestoringstep divstep(WM[i], XQM[i], DAbsBM, WM[i+1], XQM[i+1]); intdivrestoringstep divstep(WM[i], XQM[i], DAbsBM, WM[i+1], XQM[i+1]);
endgenerate
// On final setp of signed operations, negate outputs as needed to get correct sign // On final setp of signed operations, negate outputs as needed to get correct sign
neg #(`XLEN) qneg(XQM[0], XQnM); neg #(`XLEN) qneg(XQM[0], XQnM);

9
pipelined/src/muldiv/mul.sv
View File

@ -49,8 +49,8 @@ module mul (
// Signed * Unsigned = P' + ( PA - PB)*2^(XLEN-1) - PP*2^(2XLEN-2) // Signed * Unsigned = P' + ( PA - PB)*2^(XLEN-1) - PP*2^(2XLEN-2)
// Unsigned * Unsigned = P' + ( PA + PB)*2^(XLEN-1) + PP*2^(2XLEN-2) // Unsigned * Unsigned = P' + ( PA + PB)*2^(XLEN-1) + PP*2^(2XLEN-2)
logic [`XLEN*2-1:0] PP0E, PP1E, PP2E, PP3E, PP4E; logic [`XLEN*2-1:0] PP1E, PP2E, PP3E, PP4E;
logic [`XLEN*2-1:0] PP0M, PP1M, PP2M, PP3M, PP4M; logic [`XLEN*2-1:0] PP1M, PP2M, PP3M, PP4M;
logic [`XLEN-2:0] PA, PB; logic [`XLEN-2:0] PA, PB;
logic PP; logic PP;
logic MULH, MULHSU; logic MULH, MULHSU;
@ -62,7 +62,7 @@ module mul (
assign Aprime = {1'b0, ForwardedSrcAE[`XLEN-2:0]}; assign Aprime = {1'b0, ForwardedSrcAE[`XLEN-2:0]};
assign Bprime = {1'b0, ForwardedSrcBE[`XLEN-2:0]}; assign Bprime = {1'b0, ForwardedSrcBE[`XLEN-2:0]};
redundantmul #(`XLEN) bigmul(.a(Aprime), .b(Bprime), .out0(PP0E), .out1(PP1E)); assign PP1E = Aprime * Bprime;
assign PA = {(`XLEN-1){ForwardedSrcAE[`XLEN-1]}} & ForwardedSrcBE[`XLEN-2:0]; assign PA = {(`XLEN-1){ForwardedSrcAE[`XLEN-1]}} & ForwardedSrcBE[`XLEN-2:0];
assign PB = {(`XLEN-1){ForwardedSrcBE[`XLEN-1]}} & ForwardedSrcAE[`XLEN-2:0]; assign PB = {(`XLEN-1){ForwardedSrcBE[`XLEN-1]}} & ForwardedSrcAE[`XLEN-2:0];
assign PP = ForwardedSrcAE[`XLEN-1] & ForwardedSrcBE[`XLEN-1]; assign PP = ForwardedSrcAE[`XLEN-1] & ForwardedSrcBE[`XLEN-1];
@ -83,12 +83,11 @@ module mul (
// Memory Stage: Sum partial proudcts // Memory Stage: Sum partial proudcts
////////////////////////////// //////////////////////////////
flopenrc #(`XLEN*2) PP0Reg(clk, reset, FlushM, ~StallM, PP0E, PP0M);
flopenrc #(`XLEN*2) PP1Reg(clk, reset, FlushM, ~StallM, PP1E, PP1M); flopenrc #(`XLEN*2) PP1Reg(clk, reset, FlushM, ~StallM, PP1E, PP1M);
flopenrc #(`XLEN*2) PP2Reg(clk, reset, FlushM, ~StallM, PP2E, PP2M); flopenrc #(`XLEN*2) PP2Reg(clk, reset, FlushM, ~StallM, PP2E, PP2M);
flopenrc #(`XLEN*2) PP3Reg(clk, reset, FlushM, ~StallM, PP3E, PP3M); flopenrc #(`XLEN*2) PP3Reg(clk, reset, FlushM, ~StallM, PP3E, PP3M);
flopenrc #(`XLEN*2) PP4Reg(clk, reset, FlushM, ~StallM, PP4E, PP4M); flopenrc #(`XLEN*2) PP4Reg(clk, reset, FlushM, ~StallM, PP4E, PP4M);
assign ProdM = PP0M + PP1M + PP2M + PP3M + PP4M; //ForwardedSrcAE * ForwardedSrcBE; assign ProdM = PP1M + PP2M + PP3M + PP4M; //ForwardedSrcAE * ForwardedSrcBE;
endmodule endmodule

2
pipelined/src/muldiv/muldiv.sv
View File

@ -74,13 +74,11 @@ module muldiv (
// Handle sign extension for W-type instructions // Handle sign extension for W-type instructions
flopenrc #(1) W64MReg(clk, reset, FlushM, ~StallM, W64E, W64M); flopenrc #(1) W64MReg(clk, reset, FlushM, ~StallM, W64E, W64M);
generate
if (`XLEN == 64) begin:resmux // RV64 has W-type instructions if (`XLEN == 64) begin:resmux // RV64 has W-type instructions
assign MulDivResultM = W64M ? {{32{PrelimResultM[31]}}, PrelimResultM[31:0]} : PrelimResultM; assign MulDivResultM = W64M ? {{32{PrelimResultM[31]}}, PrelimResultM[31:0]} : PrelimResultM;
end else begin:resmux // RV32 has no W-type instructions end else begin:resmux // RV32 has no W-type instructions
assign MulDivResultM = PrelimResultM; assign MulDivResultM = PrelimResultM;
end end
endgenerate
// Writeback stage pipeline register // Writeback stage pipeline register
flopenrc #(`XLEN) MulDivResultWReg(clk, reset, FlushW, ~StallW, MulDivResultM, MulDivResultW); flopenrc #(`XLEN) MulDivResultWReg(clk, reset, FlushW, ~StallW, MulDivResultM, MulDivResultW);

8
pipelined/src/privileged/csrc.sv
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@ -56,7 +56,6 @@ module csrc #(parameter
output logic IllegalCSRCAccessM output logic IllegalCSRCAccessM
); );
generate
if (`ZICOUNTERS_SUPPORTED) begin:counters if (`ZICOUNTERS_SUPPORTED) begin:counters
(* mark_debug = "true" *) logic [63:0] CYCLE_REGW, INSTRET_REGW; (* mark_debug = "true" *) logic [63:0] CYCLE_REGW, INSTRET_REGW;
logic [63:0] CYCLEPlusM, INSTRETPlusM; logic [63:0] CYCLEPlusM, INSTRETPlusM;
@ -82,9 +81,9 @@ module csrc #(parameter
assign CounterEvent[0] = 1'b1; // MCYCLE always increments assign CounterEvent[0] = 1'b1; // MCYCLE always increments
assign CounterEvent[1] = 1'b0; // Counter 0 doesn't exist assign CounterEvent[1] = 1'b0; // Counter 0 doesn't exist
assign CounterEvent[2] = InstrValidNotFlushedM; assign CounterEvent[2] = InstrValidNotFlushedM;
if(`QEMU) begin // No other performance counters in QEMU if(`QEMU) begin: cevent // No other performance counters in QEMU
assign CounterEvent[`COUNTERS-1:3] = 0; assign CounterEvent[`COUNTERS-1:3] = 0;
end else begin // User-defined counters end else begin: cevent // User-defined counters
assign CounterEvent[3] = LoadStallM; // don't want to suppress on flush as this only happens if flushed. assign CounterEvent[3] = LoadStallM; // don't want to suppress on flush as this only happens if flushed.
assign CounterEvent[4] = BPPredDirWrongM & InstrValidNotFlushedM; assign CounterEvent[4] = BPPredDirWrongM & InstrValidNotFlushedM;
assign CounterEvent[5] = InstrClassM[0] & InstrValidNotFlushedM; assign CounterEvent[5] = InstrClassM[0] & InstrValidNotFlushedM;
@ -99,7 +98,7 @@ module csrc #(parameter
end end
// Counter update and write logic // Counter update and write logic
for (i = 0; i < `COUNTERS; i = i+1) begin for (i = 0; i < `COUNTERS; i = i+1) begin:cntr
assign WriteHPMCOUNTERM[i] = CSRMWriteM & (CSRAdrM == MHPMCOUNTERBASE + i); assign WriteHPMCOUNTERM[i] = CSRMWriteM & (CSRAdrM == MHPMCOUNTERBASE + i);
assign NextHPMCOUNTERM[i][`XLEN-1:0] = WriteHPMCOUNTERM[i] ? CSRWriteValM : HPMCOUNTERPlusM[i][`XLEN-1:0]; assign NextHPMCOUNTERM[i][`XLEN-1:0] = WriteHPMCOUNTERM[i] ? CSRWriteValM : HPMCOUNTERPlusM[i][`XLEN-1:0];
always_ff @(posedge clk) //, posedge reset) // ModelSim doesn't like syntax of passing array element to flop always_ff @(posedge clk) //, posedge reset) // ModelSim doesn't like syntax of passing array element to flop
@ -160,7 +159,6 @@ module csrc #(parameter
assign CSRCReadValM = 0; assign CSRCReadValM = 0;
assign IllegalCSRCAccessM = 1; // counters aren't enabled assign IllegalCSRCAccessM = 1; // counters aren't enabled
end end
endgenerate
endmodule endmodule
// To Do: // To Do:

4
pipelined/src/privileged/csri.sv
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@ -70,7 +70,6 @@ module csri #(parameter
// MEIP, MTIP, MSIP are read-only // MEIP, MTIP, MSIP are read-only
// SEIP, STIP, SSIP is writable in MIP if S mode exists // SEIP, STIP, SSIP is writable in MIP if S mode exists
// SSIP is writable in SIP if S mode exists // SSIP is writable in SIP if S mode exists
generate
if (`S_SUPPORTED) begin:mask if (`S_SUPPORTED) begin:mask
assign MIP_WRITE_MASK = 12'h222; // SEIP, STIP, SSIP are writable in MIP (20210108-draft 3.1.9) assign MIP_WRITE_MASK = 12'h222; // SEIP, STIP, SSIP are writable in MIP (20210108-draft 3.1.9)
assign SIP_WRITE_MASK = 12'h002; // SSIP is writable in SIP (privileged 20210108-draft 4.1.3) assign SIP_WRITE_MASK = 12'h002; // SSIP is writable in SIP (privileged 20210108-draft 4.1.3)
@ -89,10 +88,8 @@ module csri #(parameter
else if (WriteMIEM) IE_REGW <= (CSRWriteValM[11:0] & 12'hAAA); // MIE controls M and S fields else if (WriteMIEM) IE_REGW <= (CSRWriteValM[11:0] & 12'hAAA); // MIE controls M and S fields
else if (WriteSIEM) IE_REGW <= (CSRWriteValM[11:0] & 12'h222) | (IE_REGW & 12'h888); // only S fields else if (WriteSIEM) IE_REGW <= (CSRWriteValM[11:0] & 12'h222) | (IE_REGW & 12'h888); // only S fields
// else if (WriteUIEM) IE_REGW = (CSRWriteValM & 12'h111) | (IE_REGW & 12'hAAA); // only U field // else if (WriteUIEM) IE_REGW = (CSRWriteValM & 12'h111) | (IE_REGW & 12'hAAA); // only U field
endgenerate
// restricted views of registers // restricted views of registers
generate
always_comb begin:regs always_comb begin:regs
// Add MEIP read-only signal // Add MEIP read-only signal
IP_REGW = {IntInM[11],1'b0,IP_REGW_writeable}; IP_REGW = {IntInM[11],1'b0,IP_REGW_writeable};
@ -119,5 +116,4 @@ module csri #(parameter
UIE_REGW = 12'b0; UIE_REGW = 12'b0;
end */ end */
end end
endgenerate
endmodule endmodule

8
pipelined/src/privileged/csrm.sv
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@ -92,7 +92,6 @@ module csrm #(parameter
// There are PMP_ENTRIES = 0, 16, or 64 PMPADDR registers, each of which has its own flop // There are PMP_ENTRIES = 0, 16, or 64 PMPADDR registers, each of which has its own flop
genvar i; genvar i;
generate
if (`PMP_ENTRIES > 0) begin:pmp if (`PMP_ENTRIES > 0) begin:pmp
logic [`PMP_ENTRIES-1:0] WritePMPCFGM; logic [`PMP_ENTRIES-1:0] WritePMPCFGM;
logic [`PMP_ENTRIES-1:0] WritePMPADDRM ; logic [`PMP_ENTRIES-1:0] WritePMPADDRM ;
@ -117,7 +116,6 @@ module csrm #(parameter
end end
end end
end end
endgenerate
localparam MISA_26 = (`MISA) & 32'h03ffffff; localparam MISA_26 = (`MISA) & 32'h03ffffff;
@ -143,7 +141,6 @@ module csrm #(parameter
// CSRs // CSRs
flopenr #(`XLEN) MTVECreg(clk, reset, WriteMTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, MTVEC_REGW); //busybear: changed reset value to 0 flopenr #(`XLEN) MTVECreg(clk, reset, WriteMTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, MTVEC_REGW); //busybear: changed reset value to 0
generate
if (`S_SUPPORTED | (`U_SUPPORTED & `N_SUPPORTED)) begin:deleg // DELEG registers should exist if (`S_SUPPORTED | (`U_SUPPORTED & `N_SUPPORTED)) begin:deleg // DELEG registers should exist
flopenr #(`XLEN) MEDELEGreg(clk, reset, WriteMEDELEGM, CSRWriteValM & MEDELEG_MASK /*12'h7FF*/, MEDELEG_REGW); flopenr #(`XLEN) MEDELEGreg(clk, reset, WriteMEDELEGM, CSRWriteValM & MEDELEG_MASK /*12'h7FF*/, MEDELEG_REGW);
flopenr #(`XLEN) MIDELEGreg(clk, reset, WriteMIDELEGM, CSRWriteValM & MIDELEG_MASK /*12'h222*/, MIDELEG_REGW); flopenr #(`XLEN) MIDELEGreg(clk, reset, WriteMIDELEGM, CSRWriteValM & MIDELEG_MASK /*12'h222*/, MIDELEG_REGW);
@ -151,20 +148,17 @@ module csrm #(parameter
assign MEDELEG_REGW = 0; assign MEDELEG_REGW = 0;
assign MIDELEG_REGW = 0; assign MIDELEG_REGW = 0;
end end
endgenerate
flopenr #(`XLEN) MSCRATCHreg(clk, reset, WriteMSCRATCHM, CSRWriteValM, MSCRATCH_REGW); flopenr #(`XLEN) MSCRATCHreg(clk, reset, WriteMSCRATCHM, CSRWriteValM, MSCRATCH_REGW);
flopenr #(`XLEN) MEPCreg(clk, reset, WriteMEPCM, NextEPCM, MEPC_REGW); flopenr #(`XLEN) MEPCreg(clk, reset, WriteMEPCM, NextEPCM, MEPC_REGW);
flopenr #(`XLEN) MCAUSEreg(clk, reset, WriteMCAUSEM, NextCauseM, MCAUSE_REGW); flopenr #(`XLEN) MCAUSEreg(clk, reset, WriteMCAUSEM, NextCauseM, MCAUSE_REGW);
if(`QEMU) assign MTVAL_REGW = `XLEN'b0; if(`QEMU) assign MTVAL_REGW = `XLEN'b0;
else flopenr #(`XLEN) MTVALreg(clk, reset, WriteMTVALM, NextMtvalM, MTVAL_REGW); else flopenr #(`XLEN) MTVALreg(clk, reset, WriteMTVALM, NextMtvalM, MTVAL_REGW);
generate // *** needs comment about bit 1 if (`BUSYBEAR == 1) begin:counters // counter 1 (TIME) enable tied to 0 to match simulator***
if (`BUSYBEAR == 1) begin:counters
flopenr #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, {CSRWriteValM[31:2],1'b0,CSRWriteValM[0]}, MCOUNTEREN_REGW); flopenr #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, {CSRWriteValM[31:2],1'b0,CSRWriteValM[0]}, MCOUNTEREN_REGW);
end else begin:counters end else begin:counters
flopenr #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], MCOUNTEREN_REGW); flopenr #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], MCOUNTEREN_REGW);
end end
endgenerate
flopenr #(32) MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], MCOUNTINHIBIT_REGW); flopenr #(32) MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], MCOUNTINHIBIT_REGW);

4
pipelined/src/privileged/csrn.sv
View File

@ -49,8 +49,7 @@ module csrn #(parameter
); );
// User mode CSRs below only needed when user mode traps are supported // User mode CSRs below only needed when user mode traps are supported
generate if (`N_SUPPORTED) begin:nmode // depricated; consider removing***
if (`N_SUPPORTED) begin:nmode
logic WriteUTVECM; logic WriteUTVECM;
logic WriteUSCRATCHM, WriteUEPCM; logic WriteUSCRATCHM, WriteUEPCM;
logic WriteUCAUSEM, WriteUTVALM; logic WriteUCAUSEM, WriteUTVALM;
@ -96,5 +95,4 @@ module csrn #(parameter
assign UTVEC_REGW = 0; assign UTVEC_REGW = 0;
assign IllegalCSRNAccessM = 1; assign IllegalCSRNAccessM = 1;
end end
endgenerate
endmodule endmodule

2
pipelined/src/privileged/csrs.sv
View File

@ -69,7 +69,6 @@ module csrs #(parameter
//logic [`XLEN-1:0] SEDELEG_MASK = ~(zero | 3'b111 << 9); // sedeleg[11:9] hardwired to zero per Privileged Spec 3.1.8 //logic [`XLEN-1:0] SEDELEG_MASK = ~(zero | 3'b111 << 9); // sedeleg[11:9] hardwired to zero per Privileged Spec 3.1.8
// Supervisor mode CSRs sometimes supported // Supervisor mode CSRs sometimes supported
generate
if (`S_SUPPORTED) begin:csrs if (`S_SUPPORTED) begin:csrs
logic WriteSTVECM; logic WriteSTVECM;
logic WriteSSCRATCHM, WriteSEPCM; logic WriteSSCRATCHM, WriteSEPCM;
@ -153,5 +152,4 @@ module csrs #(parameter
assign SATP_REGW = 0; assign SATP_REGW = 0;
assign IllegalCSRSAccessM = 1; assign IllegalCSRSAccessM = 1;
end end
endgenerate
endmodule endmodule

4
pipelined/src/privileged/csrsr.sv
View File

@ -50,7 +50,6 @@ module csrsr (
// See Privileged Spec Section 3.1.6 // See Privileged Spec Section 3.1.6
// Lower privilege status registers are a subset of the full status register // Lower privilege status registers are a subset of the full status register
// *** consider adding MBE, SBE, UBE fields later from 20210108 draft spec // *** consider adding MBE, SBE, UBE fields later from 20210108 draft spec
generate
if (`XLEN==64) begin: csrsr64 // RV64 if (`XLEN==64) begin: csrsr64 // RV64
assign MSTATUS_REGW = {STATUS_SD, 27'b0, STATUS_SXL, STATUS_UXL, 9'b0, assign MSTATUS_REGW = {STATUS_SD, 27'b0, STATUS_SXL, STATUS_UXL, 9'b0,
STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV, STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV,
@ -83,10 +82,8 @@ module csrsr (
/*STATUS_SPP, STATUS_MPIE, 1'b0 2'b0, STATUS_SPIE,*/ STATUS_UPIE, /*STATUS_SPP, STATUS_MPIE, 1'b0 2'b0, STATUS_SPIE,*/ STATUS_UPIE,
/*STATUS_MIE, 1'b0*/ 3'b0, /*STATUS_SIE, */STATUS_UIE}; /*STATUS_MIE, 1'b0*/ 3'b0, /*STATUS_SIE, */STATUS_UIE};
end end
endgenerate
// harwired STATUS bits // harwired STATUS bits
generate
assign STATUS_TSR = `S_SUPPORTED & STATUS_TSR_INT; // override reigster with 0 if supervisor mode not supported assign STATUS_TSR = `S_SUPPORTED & STATUS_TSR_INT; // override reigster with 0 if supervisor mode not supported
assign STATUS_TW = (`S_SUPPORTED | `U_SUPPORTED) & STATUS_TW_INT; // override reigster with 0 if only machine mode supported assign STATUS_TW = (`S_SUPPORTED | `U_SUPPORTED) & STATUS_TW_INT; // override reigster with 0 if only machine mode supported
assign STATUS_TVM = `S_SUPPORTED & STATUS_TVM_INT; // override reigster with 0 if supervisor mode not supported assign STATUS_TVM = `S_SUPPORTED & STATUS_TVM_INT; // override reigster with 0 if supervisor mode not supported
@ -97,7 +94,6 @@ module csrsr (
assign STATUS_SUM = `S_SUPPORTED & `MEM_VIRTMEM & STATUS_SUM_INT; // override reigster with 0 if supervisor mode not supported assign STATUS_SUM = `S_SUPPORTED & `MEM_VIRTMEM & STATUS_SUM_INT; // override reigster with 0 if supervisor mode not supported
assign STATUS_MPRV = `U_SUPPORTED & STATUS_MPRV_INT; // override with 0 if user mode not supported assign STATUS_MPRV = `U_SUPPORTED & STATUS_MPRV_INT; // override with 0 if user mode not supported
assign STATUS_FS = (`S_SUPPORTED & (`F_SUPPORTED | `D_SUPPORTED)) ? STATUS_FS_INT : 2'b00; // off if no FP assign STATUS_FS = (`S_SUPPORTED & (`F_SUPPORTED | `D_SUPPORTED)) ? STATUS_FS_INT : 2'b00; // off if no FP
endgenerate
assign STATUS_SD = (STATUS_FS == 2'b11) | (STATUS_XS == 2'b11); // dirty state logic assign STATUS_SD = (STATUS_FS == 2'b11) | (STATUS_XS == 2'b11); // dirty state logic
assign STATUS_XS = 2'b00; // No additional user-mode state to be dirty assign STATUS_XS = 2'b00; // No additional user-mode state to be dirty

2
pipelined/src/privileged/csru.sv
View File

@ -44,7 +44,6 @@ module csru #(parameter
); );
// Floating Point CSRs in User Mode only needed if Floating Point is supported // Floating Point CSRs in User Mode only needed if Floating Point is supported
generate
if (`F_SUPPORTED | `D_SUPPORTED) begin:csru if (`F_SUPPORTED | `D_SUPPORTED) begin:csru
logic [4:0] FFLAGS_REGW; logic [4:0] FFLAGS_REGW;
logic [2:0] NextFRMM; logic [2:0] NextFRMM;
@ -81,5 +80,4 @@ module csru #(parameter
assign CSRUReadValM = 0; assign CSRUReadValM = 0;
assign IllegalCSRUAccessM = 1; assign IllegalCSRUAccessM = 1;
end end
endgenerate
endmodule endmodule

2
pipelined/src/privileged/trap.sv
View File

@ -103,7 +103,6 @@ module trap (
// > implemented without a hardware adder circuit. // > implemented without a hardware adder circuit.
// For example, we could require m/stvec be aligned on 7 bits to let us replace the adder directly below with // For example, we could require m/stvec be aligned on 7 bits to let us replace the adder directly below with
// [untested] PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:7], CauseM[3:0], 4'b0000} // [untested] PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:7], CauseM[3:0], 4'b0000}
generate
if(`VECTORED_INTERRUPTS_SUPPORTED) begin:vec if(`VECTORED_INTERRUPTS_SUPPORTED) begin:vec
always_comb always_comb
if (PrivilegedTrapVector[1:0] == 2'b01 & CauseM[`XLEN-1] == 1) if (PrivilegedTrapVector[1:0] == 2'b01 & CauseM[`XLEN-1] == 1)
@ -114,7 +113,6 @@ module trap (
else begin else begin
assign PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2], 2'b00}; assign PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2], 2'b00};
end end
endgenerate
always_comb always_comb
if (mretM) PrivilegedNextPCM = MEPC_REGW; if (mretM) PrivilegedNextPCM = MEPC_REGW;

14
pipelined/src/uncore/clint.sv
View File

@ -55,12 +55,8 @@ module clint (
assign HREADYCLINT = 1'b1; // *** needs to depend on DONE during accesses assign HREADYCLINT = 1'b1; // *** needs to depend on DONE during accesses
// word aligned reads // word aligned reads
generate if (`XLEN==64) assign #2 entry = {HADDR[15:3], 3'b000};
if (`XLEN==64) else assign #2 entry = {HADDR[15:2], 2'b00};
assign #2 entry = {HADDR[15:3], 3'b000};
else
assign #2 entry = {HADDR[15:2], 2'b00};
endgenerate
// DH 2/20/21: Eventually allow MTIME to run off a separate clock // DH 2/20/21: Eventually allow MTIME to run off a separate clock
// This will require synchronizing MTIME to the system clock // This will require synchronizing MTIME to the system clock
@ -69,7 +65,6 @@ module clint (
// Use req and ack signals synchronized across the clock domains. // Use req and ack signals synchronized across the clock domains.
// register access // register access
generate
if (`XLEN==64) begin:clint // 64-bit if (`XLEN==64) begin:clint // 64-bit
always @(posedge HCLK) begin always @(posedge HCLK) begin
case(entry) case(entry)
@ -136,7 +131,6 @@ module clint (
MTIME[63:32]<= HWDATA; MTIME[63:32]<= HWDATA;
end else MTIME <= MTIME + 1; end else MTIME <= MTIME + 1;
end end
endgenerate
// Software interrupt when MSIP is set // Software interrupt when MSIP is set
assign SwIntM = MSIP; assign SwIntM = MSIP;
@ -234,13 +228,9 @@ module graytobinary #(parameter N = `XLEN) (
// B[N-1] = G[N-1]; B[i] = G[i] ^ B[i+1] for 0 <= i < N-1 // B[N-1] = G[N-1]; B[i] = G[i] ^ B[i+1] for 0 <= i < N-1
// requires rippling through N-1 XOR gates // requires rippling through N-1 XOR gates
generate
begin
genvar i; genvar i;
assign b[N-1] = g[N-1]; assign b[N-1] = g[N-1];
for (i=N-2; i >= 0; i--) begin:g2b for (i=N-2; i >= 0; i--) begin:g2b
assign b[i] = g[i] ^ b[i+1]; assign b[i] = g[i] ^ b[i+1];
end end
end
endgenerate
endmodule endmodule

31
pipelined/src/uncore/gpio.sv
View File

@ -61,23 +61,13 @@ module gpio (
// account for subword read/write circuitry // account for subword read/write circuitry
// -- Note GPIO registers are 32 bits no matter what; access them with LW SW. // -- Note GPIO registers are 32 bits no matter what; access them with LW SW.
// (At least that's what I think when FE310 spec says "only naturally aligned 32-bit accesses are supported") // (At least that's what I think when FE310 spec says "only naturally aligned 32-bit accesses are supported")
generate if (`XLEN == 64) begin
if (`XLEN == 64) begin:gpio assign Din = entryd[2] ? HWDATA[63:32] : HWDATA[31:0];
always_comb assign HREADGPIO = entryd[2] ? {Dout,32'b0} : {32'b0,Dout};
if (entryd[2]) begin end else begin // 32-bit
Din = HWDATA[63:32]; assign Din = HWDATA[31:0];
HREADGPIO = {Dout,32'b0}; assign HREADGPIO = Dout;
end else begin
Din = HWDATA[31:0];
HREADGPIO = {32'b0,Dout};
end end
end else begin:gpio // 32-bit
always_comb begin
Din = HWDATA[31:0];
HREADGPIO = Dout;
end
end
endgenerate
// register access // register access
always_ff @(posedge HCLK, negedge HRESETn) begin always_ff @(posedge HCLK, negedge HRESETn) begin
@ -150,12 +140,9 @@ module gpio (
end end
// chip i/o // chip i/o
generate // connect OUT to IN for loopback testing
if (`GPIO_LOOPBACK_TEST) // connect OUT to IN for loopback testing if (`GPIO_LOOPBACK_TEST) assign input0d = GPIOPinsOut & input_en & output_en;
assign input0d = GPIOPinsOut & input_en & output_en; else assign input0d = GPIOPinsIn & input_en;
else
assign input0d = GPIOPinsIn & input_en;
endgenerate
flop #(32) sync1(HCLK,input0d,input1d); flop #(32) sync1(HCLK,input0d,input1d);
flop #(32) sync2(HCLK,input1d,input2d); flop #(32) sync2(HCLK,input1d,input2d);
flop #(32) sync3(HCLK,input2d,input3d); flop #(32) sync3(HCLK,input2d,input3d);

28
pipelined/src/uncore/plic.sv
View File

@ -77,23 +77,13 @@ module plic (
// account for subword read/write circuitry // account for subword read/write circuitry
// -- Note PLIC registers are 32 bits no matter what; access them with LW SW. // -- Note PLIC registers are 32 bits no matter what; access them with LW SW.
generate if (`XLEN == 64) begin
if (`XLEN == 64) begin:plic assign Din = entryd[2] ? HWDATA[63:32] : HWDATA[31:0];
always_comb assign HREADPLIC = entryd[2] ? {Dout,32'b0} : {32'b0,Dout};
if (entryd[2]) begin end else begin // 32-bit
Din = HWDATA[63:32]; assign Din = HWDATA[31:0];
HREADPLIC = {Dout,32'b0}; assign HREADPLIC = Dout;
end else begin
Din = HWDATA[31:0];
HREADPLIC = {32'b0,Dout};
end end
end else begin:plic // 32-bit
always_comb begin
Din = HWDATA[31:0];
HREADPLIC = Dout;
end
end
endgenerate
// ================== // ==================
// Register Interface // Register Interface
@ -165,14 +155,11 @@ module plic (
// pending array - indexed by priority_lvl x source_ID // pending array - indexed by priority_lvl x source_ID
genvar i, j; genvar i, j;
generate
for (j=1; j<=7; j++) begin: pending for (j=1; j<=7; j++) begin: pending
for (i=1; i<=N; i=i+1) begin: pendingbit for (i=1; i<=N; i=i+1) begin: pendingbit
// *** make sure that this synthesizes into N decoders, not 7*N 3-bit equality comparators (right?)
assign pendingArray[j][i] = (intPriority[i]==j) & intEn[i] & intPending[i]; assign pendingArray[j][i] = (intPriority[i]==j) & intEn[i] & intPending[i];
end end
end end
endgenerate
// pending array, except grouped by priority // pending array, except grouped by priority
assign pendingPGrouped[7:1] = {|pendingArray[7], assign pendingPGrouped[7:1] = {|pendingArray[7],
|pendingArray[6], |pendingArray[6],
@ -200,8 +187,7 @@ module plic (
| ({N{pendingMaxP[2]}} & pendingArray[2]) | ({N{pendingMaxP[2]}} & pendingArray[2])
| ({N{pendingMaxP[1]}} & pendingArray[1]); | ({N{pendingMaxP[1]}} & pendingArray[1]);
// find the lowest ID amongst active interrupts at the highest priority // find the lowest ID amongst active interrupts at the highest priority
int k; int k; // *** rewrite as priority encoder
// *** verify that this synthesizes to a reasonable priority encoder and that k doesn't actually exist in hardware
always_comb begin always_comb begin
intClaim = 6'b0; intClaim = 6'b0;
for(k=N; k>0; k=k-1) begin for(k=N; k>0; k=k-1) begin

10
pipelined/src/uncore/ram.sv
View File

@ -49,11 +49,9 @@ module ram #(parameter BASE=0, RANGE = 65535) (
logic memwrite; logic memwrite;
logic [3:0] busycount; logic [3:0] busycount;
generate
if(`FPGA) begin:ram if(`FPGA) begin:ram
initial begin initial begin
//$readmemh(PRELOAD, RAM); //$readmemh(PRELOAD, RAM);
// FPGA only
RAM[0] = 64'h94e1819300002197; RAM[0] = 64'h94e1819300002197;
RAM[1] = 64'h4281420141014081; RAM[1] = 64'h4281420141014081;
RAM[2] = 64'h4481440143814301; RAM[2] = 64'h4481440143814301;
@ -98,7 +96,6 @@ module ram #(parameter BASE=0, RANGE = 65535) (
RAM[41] = 64'h0000808210a7a023; RAM[41] = 64'h0000808210a7a023;
end // initial begin end // initial begin
end // if (FPGA) end // if (FPGA)
endgenerate
assign initTrans = HREADY & HSELRam & (HTRANS != 2'b00); assign initTrans = HREADY & HSELRam & (HTRANS != 2'b00);
@ -144,26 +141,23 @@ module ram #(parameter BASE=0, RANGE = 65535) (
-----/\----- EXCLUDED -----/\----- */ -----/\----- EXCLUDED -----/\----- */
/* verilator lint_off WIDTH */ /* verilator lint_off WIDTH */
generate if (`XLEN == 64) begin:ramrw
if (`XLEN == 64) begin:ramrd
always_ff @(posedge HCLK) begin always_ff @(posedge HCLK) begin
HWADDR <= #1 A; HWADDR <= #1 A;
HREADRam0 <= #1 RAM[A[31:3]]; HREADRam0 <= #1 RAM[A[31:3]];
if (memwrite & risingHREADYRam) RAM[HWADDR[31:3]] <= #1 HWDATA; if (memwrite & risingHREADYRam) RAM[HWADDR[31:3]] <= #1 HWDATA;
end end
end else begin end else begin
always_ff @(posedge HCLK) begin:ramrd always_ff @(posedge HCLK) begin:ramrw
HWADDR <= #1 A; HWADDR <= #1 A;
HREADRam0 <= #1 RAM[A[31:2]]; HREADRam0 <= #1 RAM[A[31:2]];
if (memwrite & risingHREADYRam) RAM[HWADDR[31:2]] <= #1 HWDATA; if (memwrite & risingHREADYRam) RAM[HWADDR[31:2]] <= #1 HWDATA;
end end
end end
endgenerate
/* verilator lint_on WIDTH */ /* verilator lint_on WIDTH */
//assign HREADRam = HREADYRam ? HREADRam0 : `XLEN'bz; //assign HREADRam = HREADYRam ? HREADRam0 : `XLEN'bz;
// *** Ross Thompson: removed tristate as fpga synthesis removes. // *** Ross Thompson: removed tristate as fpga synthesis removes.
assign HREADRam = HREADRam0; assign HREADRam = HREADRam0;
endmodule endmodule

6
pipelined/src/uncore/sdc/SDC.sv
View File

@ -156,7 +156,6 @@ module SDC
flopenl #(3) CommandReg(HCLK, ~HRESETn, (HADDRDelay == 'h8 & RegWrite) | (CommandCompleted), flopenl #(3) CommandReg(HCLK, ~HRESETn, (HADDRDelay == 'h8 & RegWrite) | (CommandCompleted),
CommandCompleted ? '0 : HWDATA[2:0], '0, Command); CommandCompleted ? '0 : HWDATA[2:0], '0, Command);
generate
if (`XLEN == 64) begin if (`XLEN == 64) begin
flopenr #(64-9) AddressReg(HCLK, ~HRESETn, (HADDRDelay == 'h10 & RegWrite), flopenr #(64-9) AddressReg(HCLK, ~HRESETn, (HADDRDelay == 'h10 & RegWrite),
HWDATA[`XLEN-1:9], Address); HWDATA[`XLEN-1:9], Address);
@ -166,7 +165,6 @@ module SDC
flopenr #(32) AddressHighReg(HCLK, ~HRESETn, (HADDRDelay == 'h14 & RegWrite), flopenr #(32) AddressHighReg(HCLK, ~HRESETn, (HADDRDelay == 'h14 & RegWrite),
HWDATA, Address[63:32]); HWDATA, Address[63:32]);
end end
endgenerate
flopen #(`XLEN) DataReg(HCLK, (HADDRDelay == 'h18 & RegWrite), flopen #(`XLEN) DataReg(HCLK, (HADDRDelay == 'h18 & RegWrite),
HWDATA, SDCWriteData); HWDATA, SDCWriteData);
@ -175,7 +173,6 @@ module SDC
assign Status = {ErrorCode, InvalidCommand, SDCBusy, SDCInitialized}; assign Status = {ErrorCode, InvalidCommand, SDCBusy, SDCInitialized};
generate
if(`XLEN == 64) begin if(`XLEN == 64) begin
always_comb always_comb
case(HADDRDelay[4:0]) case(HADDRDelay[4:0])
@ -200,7 +197,6 @@ module SDC
default: HREADSDC = {24'b0, CLKDiv}; default: HREADSDC = {24'b0, CLKDiv};
endcase endcase
end end
endgenerate
for(index = 0; index < 4096/`XLEN; index++) begin for(index = 0; index < 4096/`XLEN; index++) begin
@ -208,7 +204,6 @@ module SDC
end end
assign SDCReadDataPreNibbleSwap = ReadData512ByteWords[WordCount]; assign SDCReadDataPreNibbleSwap = ReadData512ByteWords[WordCount];
generate
if(`XLEN == 64) begin if(`XLEN == 64) begin
assign SDCReadData = {SDCReadDataPreNibbleSwap[59:56], SDCReadDataPreNibbleSwap[63:60], assign SDCReadData = {SDCReadDataPreNibbleSwap[59:56], SDCReadDataPreNibbleSwap[63:60],
SDCReadDataPreNibbleSwap[51:48], SDCReadDataPreNibbleSwap[55:52], SDCReadDataPreNibbleSwap[51:48], SDCReadDataPreNibbleSwap[55:52],
@ -224,7 +219,6 @@ module SDC
SDCReadDataPreNibbleSwap[11:8], SDCReadDataPreNibbleSwap[15:12], SDCReadDataPreNibbleSwap[11:8], SDCReadDataPreNibbleSwap[15:12],
SDCReadDataPreNibbleSwap[3:0], SDCReadDataPreNibbleSwap[7:4]}; SDCReadDataPreNibbleSwap[3:0], SDCReadDataPreNibbleSwap[7:4]};
end end
endgenerate
flopenr #($clog2(4096/`XLEN)) WordCountReg flopenr #($clog2(4096/`XLEN)) WordCountReg
(.clk(HCLK), (.clk(HCLK),

15
pipelined/src/uncore/sdc/clkdivider.sv
View File

@ -88,17 +88,6 @@ module clkdivider #(parameter integer g_COUNT_WIDTH)
assign w_fd_D = ~ r_fd_Q; assign w_fd_D = ~ r_fd_Q;
if(`FPGA) BUFGMUX clkMux(.I1(r_fd_Q), .I0(i_CLK), .S(i_EN), .O(o_CLK));
generate else assign o_CLK = i_EN ? r_fd_Q : i_CLK;
if(`FPGA) begin
BUFGMUX
clkMux(.I1(r_fd_Q),
.I0(i_CLK),
.S(i_EN),
.O(o_CLK));
end else begin
assign o_CLK = i_EN ? r_fd_Q : i_CLK;
end
endgenerate
endmodule endmodule

3
pipelined/src/uncore/subwordwrite.sv
View File

@ -35,7 +35,6 @@ module subwordwrite (
logic [`XLEN-1:0] WriteDataSubwordDuplicated; logic [`XLEN-1:0] WriteDataSubwordDuplicated;
generate
if (`XLEN == 64) begin:sww if (`XLEN == 64) begin:sww
logic [7:0] ByteMaskM; logic [7:0] ByteMaskM;
// Compute write mask // Compute write mask
@ -104,6 +103,4 @@ module subwordwrite (
end end
end end
endgenerate
endmodule endmodule

2
pipelined/src/uncore/uart.sv
View File

@ -54,7 +54,6 @@ module uart (
assign HRESPUART = 0; // OK assign HRESPUART = 0; // OK
assign HREADYUART = 1; // should idle high during address phase and respond high when done; will need to be modified if UART ever needs more than 1 cycle to do something assign HREADYUART = 1; // should idle high during address phase and respond high when done; will need to be modified if UART ever needs more than 1 cycle to do something
generate
if (`XLEN == 64) begin:uart if (`XLEN == 64) begin:uart
always_comb begin always_comb begin
HREADUART = {Dout, Dout, Dout, Dout, Dout, Dout, Dout, Dout}; HREADUART = {Dout, Dout, Dout, Dout, Dout, Dout, Dout, Dout};
@ -80,7 +79,6 @@ module uart (
endcase endcase
end end
end end
endgenerate
logic BAUDOUTb; // loop tx clock BAUDOUTb back to rx clock RCLK logic BAUDOUTb; // loop tx clock BAUDOUTb back to rx clock RCLK
// *** make sure reads don't occur on UART unless fully selected because they could change state. This applies to all peripherals // *** make sure reads don't occur on UART unless fully selected because they could change state. This applies to all peripherals

21
pipelined/src/uncore/uartPC16550D.sv
View File

@ -257,12 +257,9 @@ module uartPC16550D(
else if (fifoenabled & ~rxfifoempty & rxbaudpulse & ~rxfifotimeout) rxtimeoutcnt <= #1 rxtimeoutcnt+1; // *** not right else if (fifoenabled & ~rxfifoempty & rxbaudpulse & ~rxfifotimeout) rxtimeoutcnt <= #1 rxtimeoutcnt+1; // *** not right
end end
generate // ***explain why
if(`QEMU) if(`QEMU) assign rxcentered = rxbaudpulse & (rxoversampledcnt[1:0] == 2'b10); // implies rxstate = UART_ACTIVE
assign rxcentered = rxbaudpulse & (rxoversampledcnt[1:0] == 2'b10); // implies rxstate = UART_ACTIVE else assign rxcentered = rxbaudpulse & (rxoversampledcnt == 4'b1000); // implies rxstate = UART_ACTIVE
else
assign rxcentered = rxbaudpulse & (rxoversampledcnt == 4'b1000); // implies rxstate = UART_ACTIVE
endgenerate
assign rxbitsexpected = 4'd1 + (4'd5 + {2'b00, LCR[1:0]}) + {3'b000, LCR[3]} + 4'd1; // start bit + data bits + (parity bit) + stop bit assign rxbitsexpected = 4'd1 + (4'd5 + {2'b00, LCR[1:0]}) + {3'b000, LCR[3]} + 4'd1; // start bit + data bits + (parity bit) + stop bit
@ -325,7 +322,6 @@ module uartPC16550D(
// detect any errors in rx fifo // detect any errors in rx fifo
// although rxfullbit looks like a combinational loop, in one bit rxfifotail == i and breaks the loop // although rxfullbit looks like a combinational loop, in one bit rxfifotail == i and breaks the loop
// tail is normally higher than head, but might wrap around. unwrapped variable adds 16 to eliminate wrapping // tail is normally higher than head, but might wrap around. unwrapped variable adds 16 to eliminate wrapping
generate
assign rxfifotailunwrapped = rxfifotail < rxfifohead ? {1'b1, rxfifotail} : {1'b0, rxfifotail}; assign rxfifotailunwrapped = rxfifotail < rxfifohead ? {1'b1, rxfifotail} : {1'b0, rxfifotail};
genvar i; genvar i;
for (i=0; i<32; i++) begin:rxfull for (i=0; i<32; i++) begin:rxfull
@ -340,7 +336,6 @@ module uartPC16550D(
else else
assign rxfullbit[0] = ((rxfifohead==i) | rxfullbit[15]) & (rxfifotail != i);*/ assign rxfullbit[0] = ((rxfifohead==i) | rxfullbit[15]) & (rxfifotail != i);*/
end end
endgenerate
assign rxfifohaserr = |(RXerrbit & rxfullbit); assign rxfifohaserr = |(RXerrbit & rxfullbit);
// receive buffer register and ready bit // receive buffer register and ready bit
@ -383,13 +378,9 @@ module uartPC16550D(
end end
assign txbitsexpected = 4'd1 + (4'd5 + {2'b00, LCR[1:0]}) + {3'b000, LCR[3]} + 4'd1 + {3'b000, LCR[2]} - 4'd1; // start bit + data bits + (parity bit) + stop bit(s) assign txbitsexpected = 4'd1 + (4'd5 + {2'b00, LCR[1:0]}) + {3'b000, LCR[3]} + 4'd1 + {3'b000, LCR[2]} - 4'd1; // start bit + data bits + (parity bit) + stop bit(s)
generate // *** explain; is this necessary?
if (`QEMU) if (`QEMU) assign txnextbit = txbaudpulse & (txoversampledcnt[1:0] == 2'b00); // implies txstate = UART_ACTIVE
assign txnextbit = txbaudpulse & (txoversampledcnt[1:0] == 2'b00); // implies txstate = UART_ACTIVE else assign txnextbit = txbaudpulse & (txoversampledcnt == 4'b0000); // implies txstate = UART_ACTIVE
else
assign txnextbit = txbaudpulse & (txoversampledcnt == 4'b0000); // implies txstate = UART_ACTIVE
endgenerate
/////////////////////////////////////////// ///////////////////////////////////////////
// transmit holding register, shift register, FIFO // transmit holding register, shift register, FIFO

4
pipelined/src/wally/wallypipelinedhart.sv
View File

@ -304,7 +304,6 @@ module wallypipelinedhart (
.FlushF, .FlushD, .FlushE, .FlushM, .FlushW .FlushF, .FlushD, .FlushE, .FlushM, .FlushW
); // global stall and flush control ); // global stall and flush control
generate
if (`ZICSR_SUPPORTED) begin:priv if (`ZICSR_SUPPORTED) begin:priv
privileged priv( privileged priv(
.clk, .reset, .clk, .reset,
@ -385,7 +384,4 @@ module wallypipelinedhart (
assign IllegalFPUInstrD = 1; assign IllegalFPUInstrD = 1;
assign SetFflagsM = 0; assign SetFflagsM = 0;
end end
endgenerate
// Priveleged block operates in M and W stages, handling CSRs and exceptions
endmodule endmodule

10
pipelined/testbench/common/logging.sv
View File

@ -1,10 +0,0 @@
module logging(
input logic clk, reset,
input logic [31:0] HADDR,
input logic [1:0] HTRANS);
always @(posedge clk)
if (HTRANS != 2'b00 & HADDR == 0)
$display("%t Warning: access to memory address 0\n", $realtime);
endmodule

2
pipelined/testbench/common/sdModel.sv
View File

@ -121,11 +121,9 @@ module sdModel
integer sdModel_file_desc; integer sdModel_file_desc;
genvar i; genvar i;
generate
for(i=0; i<4; i=i+1) begin:CRC_16_gen for(i=0; i<4; i=i+1) begin:CRC_16_gen
sd_crc_16 CRC_16_i (crcDat_in[i],crcDat_en, sdClk, crcDat_rst, crcDat_out[i]); sd_crc_16 CRC_16_i (crcDat_in[i],crcDat_en, sdClk, crcDat_rst, crcDat_out[i]);
end end
endgenerate
sd_crc_7 crc_7 sd_crc_7 crc_7
( (

36
pipelined/testbench/testbench-fpga.sv
View File

@ -763,17 +763,12 @@ string tests32f[] = '{
.done(DCacheFlushDone)); .done(DCacheFlushDone));
generate
// initialize the branch predictor // initialize the branch predictor
if (`BPRED_ENABLED == 1) begin : bpred if (`BPRED_ENABLED == 1)
initial begin initial begin
$readmemb(`TWO_BIT_PRELOAD, dut.wallypipelinedsoc.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem); $readmemb(`TWO_BIT_PRELOAD, dut.wallypipelinedsoc.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
$readmemb(`BTB_PRELOAD, dut.wallypipelinedsoc.hart.ifu.bpred.bpred.TargetPredictor.memory.mem); $readmemb(`BTB_PRELOAD, dut.wallypipelinedsoc.hart.ifu.bpred.bpred.TargetPredictor.memory.mem);
end end
end
endgenerate
endmodule endmodule
module riscvassertions(); module riscvassertions();
@ -783,14 +778,14 @@ module riscvassertions();
assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double without supporting float"); assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double without supporting float");
assert (`XLEN == 64 | ~`D_SUPPORTED) else $error("Wally does not yet support D extensions on RV32"); assert (`XLEN == 64 | ~`D_SUPPORTED) else $error("Wally does not yet support D extensions on RV32");
assert (`DCACHE_WAYSIZEINBYTES <= 4096 | `MEM_DCACHE == 0 | `MEM_VIRTMEM == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); assert (`DCACHE_WAYSIZEINBYTES <= 4096 | `MEM_DCACHE == 0 | `MEM_VIRTMEM == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
assert (`DCACHE_BLOCKLENINBITS >= 128 | `MEM_DCACHE == 0) else $error("DCACHE_BLOCKLENINBITS must be at least 128 when caches are enabled"); assert (`DCACHE_LINELENINBITS >= 128 | `MEM_DCACHE == 0) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
assert (`DCACHE_BLOCKLENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_BLOCKLENINBITS must be smaller than way size"); assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size");
assert (`ICACHE_WAYSIZEINBYTES <= 4096 | `MEM_ICACHE == 0 | `MEM_VIRTMEM == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); assert (`ICACHE_WAYSIZEINBYTES <= 4096 | `MEM_ICACHE == 0 | `MEM_VIRTMEM == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
assert (`ICACHE_BLOCKLENINBITS >= 32 | `MEM_ICACHE == 0) else $error("ICACHE_BLOCKLENINBITS must be at least 32 when caches are enabled"); assert (`ICACHE_LINELENINBITS >= 32 | `MEM_ICACHE == 0) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled");
assert (`ICACHE_BLOCKLENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_BLOCKLENINBITS must be smaller than way size"); assert (`ICACHE_LINELENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size");
assert (2**$clog2(`DCACHE_BLOCKLENINBITS) == `DCACHE_BLOCKLENINBITS) else $error("DCACHE_BLOCKLENINBITS must be a power of 2"); assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS) else $error("DCACHE_LINELENINBITS must be a power of 2");
assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2"); assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2");
assert (2**$clog2(`ICACHE_BLOCKLENINBITS) == `ICACHE_BLOCKLENINBITS) else $error("ICACHE_BLOCKLENINBITS must be a power of 2"); assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS) else $error("ICACHE_LINELENINBITS must be a power of 2");
assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2"); assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2");
assert (`ICACHE_NUMWAYS == 1 | `MEM_ICACHE == 0) else $warning("Multiple Instruction Cache ways not yet implemented"); assert (`ICACHE_NUMWAYS == 1 | `MEM_ICACHE == 0) else $warning("Multiple Instruction Cache ways not yet implemented");
assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES) else $error("ITLB_ENTRIES must be a power of 2"); assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES) else $error("ITLB_ENTRIES must be a power of 2");
@ -811,12 +806,12 @@ module DCacheFlushFSM
localparam integer numlines = testbench.dut.wallypipelinedsoc.hart.lsu.dcache.NUMLINES; localparam integer numlines = testbench.dut.wallypipelinedsoc.hart.lsu.dcache.NUMLINES;
localparam integer numways = testbench.dut.wallypipelinedsoc.hart.lsu.dcache.NUMWAYS; localparam integer numways = testbench.dut.wallypipelinedsoc.hart.lsu.dcache.NUMWAYS;
localparam integer blockbytelen = testbench.dut.wallypipelinedsoc.hart.lsu.dcache.BLOCKBYTELEN; localparam integer linebytelen = testbench.dut.wallypipelinedsoc.hart.lsu.dcache.LINEBYTELEN;
localparam integer numwords = testbench.dut.wallypipelinedsoc.hart.lsu.dcache.BLOCKLEN/`XLEN; localparam integer numwords = testbench.dut.wallypipelinedsoc.hart.lsu.dcache.LINELEN/`XLEN;
localparam integer lognumlines = $clog2(numlines); localparam integer lognumlines = $clog2(numlines);
localparam integer logblockbytelen = $clog2(blockbytelen); localparam integer loglinebytelen = $clog2(linebytelen);
localparam integer lognumways = $clog2(numways); localparam integer lognumways = $clog2(numways);
localparam integer tagstart = lognumlines + logblockbytelen; localparam integer tagstart = lognumlines + loglinebytelen;
@ -830,12 +825,10 @@ module DCacheFlushFSM
logic [`XLEN-1:0] ShadowRAM[`RAM_BASE>>(1+`XLEN/32):(`RAM_RANGE+`RAM_BASE)>>1+(`XLEN/32)]; logic [`XLEN-1:0] ShadowRAM[`RAM_BASE>>(1+`XLEN/32):(`RAM_RANGE+`RAM_BASE)>>1+(`XLEN/32)];
generate
for(index = 0; index < numlines; index++) begin for(index = 0; index < numlines; index++) begin
for(way = 0; way < numways; way++) begin for(way = 0; way < numways; way++) begin
for(cacheWord = 0; cacheWord < numwords; cacheWord++) begin for(cacheWord = 0; cacheWord < numwords; cacheWord++) begin
copyShadow #(.tagstart(tagstart), copyShadow #(.tagstart(tagstart), .loglinebytelen(loglinebytelen))
.logblockbytelen(logblockbytelen))
copyShadow(.clk, copyShadow(.clk,
.start, .start,
.tag(testbench.dut.wallypipelinedsoc.hart.lsu.dcache.MemWay[way].CacheTagMem.StoredData[index]), .tag(testbench.dut.wallypipelinedsoc.hart.lsu.dcache.MemWay[way].CacheTagMem.StoredData[index]),
@ -852,7 +845,6 @@ module DCacheFlushFSM
end end
end end
end end
endgenerate
integer i, j, k; integer i, j, k;
@ -879,7 +871,7 @@ module DCacheFlushFSM
endmodule endmodule
module copyShadow module copyShadow
#(parameter tagstart, logblockbytelen) #(parameter tagstart, loglinebytelen)
(input logic clk, (input logic clk,
input logic start, input logic start,
input logic [`PA_BITS-1:tagstart] tag, input logic [`PA_BITS-1:tagstart] tag,
@ -900,7 +892,7 @@ module copyShadow
CacheValid = valid; CacheValid = valid;
CacheDirty = dirty; CacheDirty = dirty;
CacheData = data; CacheData = data;
CacheAdr = (tag << tagstart) + (index << logblockbytelen) + (cacheWord << $clog2(`XLEN/8)); CacheAdr = (tag << tagstart) + (index << loglinebytelen) + (cacheWord << $clog2(`XLEN/8));
end end
end end

11
pipelined/testbench/testbench-linux.sv
View File

@ -22,7 +22,7 @@
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT // BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
// When letting Wally go for it, let wally generate own interrupts // When letting Wally go for it, let wally make own interrupts
/////////////////////////////////////////// ///////////////////////////////////////////
`include "wally-config.vh" `include "wally-config.vh"
@ -36,7 +36,7 @@
// 4: print memory accesses whenever they happen // 4: print memory accesses whenever they happen
// 5: print everything // 5: print everything
module testbench(); module testbench;
/////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////
/////////////////////////////////// CONFIG //////////////////////////////////// /////////////////////////////////// CONFIG ////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////
@ -280,13 +280,6 @@ module testbench();
`INIT_CHECKPOINT_SIMPLE_ARRAY(RF, [`XLEN-1:0],31,1); `INIT_CHECKPOINT_SIMPLE_ARRAY(RF, [`XLEN-1:0],31,1);
`INIT_CHECKPOINT_SIMPLE_ARRAY(HPMCOUNTER, [`XLEN-1:0],`COUNTERS-1,3); `INIT_CHECKPOINT_SIMPLE_ARRAY(HPMCOUNTER, [`XLEN-1:0],`COUNTERS-1,3);
generate
genvar i;
/* -----\/----- EXCLUDED -----\/-----
`INIT_CHECKPOINT_GENBLK_ARRAY(PMP_BASE, PMPCFG, [7:0],`PMP_ENTRIES-1,0);
`INIT_CHECKPOINT_GENBLK_ARRAY(PMP_BASE, PMPADDR, [`XLEN-1:0],`PMP_ENTRIES-1,0);
-----/\----- EXCLUDED -----/\----- */
endgenerate
`INIT_CHECKPOINT_VAL(PC, [`XLEN-1:0]); `INIT_CHECKPOINT_VAL(PC, [`XLEN-1:0]);
`INIT_CHECKPOINT_VAL(MEDELEG, [`XLEN-1:0]); `INIT_CHECKPOINT_VAL(MEDELEG, [`XLEN-1:0]);
`INIT_CHECKPOINT_VAL(MIDELEG, [`XLEN-1:0]); `INIT_CHECKPOINT_VAL(MIDELEG, [`XLEN-1:0]);

60
pipelined/testbench/testbench.sv
View File

@ -71,7 +71,6 @@ logic [3:0] dummy;
// check assertions for a legal configuration // check assertions for a legal configuration
riscvassertions riscvassertions(); riscvassertions riscvassertions();
logging logging(clk, reset, dut.uncore.HADDR, dut.uncore.HTRANS);
// pick tests based on modes supported // pick tests based on modes supported
initial begin initial begin
@ -88,7 +87,7 @@ logic [3:0] dummy;
"arch64d": if (`D_SUPPORTED) tests = arch64d; "arch64d": if (`D_SUPPORTED) tests = arch64d;
"imperas64i": tests = imperas64i; "imperas64i": tests = imperas64i;
"imperas64p": tests = imperas64p; "imperas64p": tests = imperas64p;
"imperas64mmu": if (`MEM_VIRTMEM) tests = imperas64mmu; // "imperas64mmu": if (`MEM_VIRTMEM) tests = imperas64mmu;
"imperas64f": if (`F_SUPPORTED) tests = imperas64f; "imperas64f": if (`F_SUPPORTED) tests = imperas64f;
"imperas64d": if (`D_SUPPORTED) tests = imperas64d; "imperas64d": if (`D_SUPPORTED) tests = imperas64d;
"imperas64m": if (`M_SUPPORTED) tests = imperas64m; "imperas64m": if (`M_SUPPORTED) tests = imperas64m;
@ -111,7 +110,7 @@ logic [3:0] dummy;
"arch32f": if (`F_SUPPORTED) tests = arch32f; "arch32f": if (`F_SUPPORTED) tests = arch32f;
"imperas32i": tests = imperas32i; "imperas32i": tests = imperas32i;
"imperas32p": tests = imperas32p; "imperas32p": tests = imperas32p;
"imperas32mmu": if (`MEM_VIRTMEM) tests = imperas32mmu; // "imperas32mmu": if (`MEM_VIRTMEM) tests = imperas32mmu;
"imperas32f": if (`F_SUPPORTED) tests = imperas32f; "imperas32f": if (`F_SUPPORTED) tests = imperas32f;
"imperas32m": if (`M_SUPPORTED) tests = imperas32m; "imperas32m": if (`M_SUPPORTED) tests = imperas32m;
"imperas32a": if (`A_SUPPORTED) tests = imperas32a; "imperas32a": if (`A_SUPPORTED) tests = imperas32a;
@ -297,13 +296,8 @@ logic [3:0] dummy;
// or sw gp, -56(t0) // or sw gp, -56(t0)
// or on a jump to self infinite loop (6f) for RISC-V Arch tests // or on a jump to self infinite loop (6f) for RISC-V Arch tests
logic ecf; // remove this once we don't rely on old Imperas tests with Ecalls logic ecf; // remove this once we don't rely on old Imperas tests with Ecalls
generate if (`ZICSR_SUPPORTED) assign ecf = dut.hart.priv.priv.EcallFaultM;
if (`ZICSR_SUPPORTED) begin else assign ecf = 0;
assign ecf = dut.hart.priv.priv.EcallFaultM;
end else begin
assign ecf = 0;
end
endgenerate
assign DCacheFlushStart = ecf & assign DCacheFlushStart = ecf &
(dut.hart.ieu.dp.regf.rf[3] == 1 | (dut.hart.ieu.dp.regf.rf[3] == 1 |
(dut.hart.ieu.dp.regf.we3 & (dut.hart.ieu.dp.regf.we3 &
@ -311,24 +305,17 @@ logic [3:0] dummy;
dut.hart.ieu.dp.regf.wd3 == 1)) | dut.hart.ieu.dp.regf.wd3 == 1)) |
(dut.hart.ifu.InstrM == 32'h6f | dut.hart.ifu.InstrM == 32'hfc32a423 | dut.hart.ifu.InstrM == 32'hfc32a823) & dut.hart.ieu.c.InstrValidM; (dut.hart.ifu.InstrM == 32'h6f | dut.hart.ifu.InstrM == 32'hfc32a423 | dut.hart.ifu.InstrM == 32'hfc32a823) & dut.hart.ieu.c.InstrValidM;
// **** Fix when the check in the shadow ram is fixed.
DCacheFlushFSM DCacheFlushFSM(.clk(clk), DCacheFlushFSM DCacheFlushFSM(.clk(clk),
.reset(reset), .reset(reset),
.start(DCacheFlushStart), .start(DCacheFlushStart),
.done(DCacheFlushDone)); .done(DCacheFlushDone));
generate
// initialize the branch predictor // initialize the branch predictor
if (`BPRED_ENABLED == 1) begin : bpred if (`BPRED_ENABLED == 1)
initial begin initial begin
$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem); $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.mem); $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.mem);
end end
end
endgenerate
endmodule endmodule
module riscvassertions; module riscvassertions;
@ -339,14 +326,14 @@ module riscvassertions;
assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double (D) without supporting float (F)"); assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double (D) without supporting float (F)");
assert (`XLEN == 64 | ~`D_SUPPORTED) else $error("Wally does not yet support D extensions on RV32"); assert (`XLEN == 64 | ~`D_SUPPORTED) else $error("Wally does not yet support D extensions on RV32");
assert (`DCACHE_WAYSIZEINBYTES <= 4096 | `MEM_DCACHE == 0 | `MEM_VIRTMEM == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); assert (`DCACHE_WAYSIZEINBYTES <= 4096 | `MEM_DCACHE == 0 | `MEM_VIRTMEM == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
assert (`DCACHE_BLOCKLENINBITS >= 128 | `MEM_DCACHE == 0) else $error("DCACHE_BLOCKLENINBITS must be at least 128 when caches are enabled"); assert (`DCACHE_LINELENINBITS >= 128 | `MEM_DCACHE == 0) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
assert (`DCACHE_BLOCKLENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_BLOCKLENINBITS must be smaller than way size"); assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size");
assert (`ICACHE_WAYSIZEINBYTES <= 4096 | `MEM_ICACHE == 0 | `MEM_VIRTMEM == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); assert (`ICACHE_WAYSIZEINBYTES <= 4096 | `MEM_ICACHE == 0 | `MEM_VIRTMEM == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
assert (`ICACHE_BLOCKLENINBITS >= 32 | `MEM_ICACHE == 0) else $error("ICACHE_BLOCKLENINBITS must be at least 32 when caches are enabled"); assert (`ICACHE_LINELENINBITS >= 32 | `MEM_ICACHE == 0) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled");
assert (`ICACHE_BLOCKLENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_BLOCKLENINBITS must be smaller than way size"); assert (`ICACHE_LINELENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size");
assert (2**$clog2(`DCACHE_BLOCKLENINBITS) == `DCACHE_BLOCKLENINBITS | `MEM_DCACHE==0) else $error("DCACHE_BLOCKLENINBITS must be a power of 2"); assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS | `MEM_DCACHE==0) else $error("DCACHE_LINELENINBITS must be a power of 2");
assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES | `MEM_DCACHE==0) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2"); assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES | `MEM_DCACHE==0) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2");
assert (2**$clog2(`ICACHE_BLOCKLENINBITS) == `ICACHE_BLOCKLENINBITS | `MEM_ICACHE==0) else $error("ICACHE_BLOCKLENINBITS must be a power of 2"); assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS | `MEM_ICACHE==0) else $error("ICACHE_LINELENINBITS must be a power of 2");
assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES | `MEM_ICACHE==0) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2"); assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES | `MEM_ICACHE==0) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2");
assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES | `MEM_VIRTMEM==0) else $error("ITLB_ENTRIES must be a power of 2"); assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES | `MEM_VIRTMEM==0) else $error("ITLB_ENTRIES must be a power of 2");
assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES | `MEM_VIRTMEM==0) else $error("DTLB_ENTRIES must be a power of 2"); assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES | `MEM_VIRTMEM==0) else $error("DTLB_ENTRIES must be a power of 2");
@ -371,16 +358,15 @@ module DCacheFlushFSM
logic [`XLEN-1:0] ShadowRAM[`RAM_BASE>>(1+`XLEN/32):(`RAM_RANGE+`RAM_BASE)>>1+(`XLEN/32)]; logic [`XLEN-1:0] ShadowRAM[`RAM_BASE>>(1+`XLEN/32):(`RAM_RANGE+`RAM_BASE)>>1+(`XLEN/32)];
generate
if(`MEM_DCACHE) begin if(`MEM_DCACHE) begin
localparam integer numlines = testbench.dut.hart.lsu.dcache.dcache.NUMLINES; localparam integer numlines = testbench.dut.hart.lsu.dcache.dcache.NUMLINES;
localparam integer numways = testbench.dut.hart.lsu.dcache.dcache.NUMWAYS; localparam integer numways = testbench.dut.hart.lsu.dcache.dcache.NUMWAYS;
localparam integer blockbytelen = testbench.dut.hart.lsu.dcache.dcache.BLOCKBYTELEN; localparam integer linebytelen = testbench.dut.hart.lsu.dcache.dcache.LINEBYTELEN;
localparam integer numwords = testbench.dut.hart.lsu.dcache.dcache.BLOCKLEN/`XLEN; localparam integer numwords = testbench.dut.hart.lsu.dcache.dcache.LINELEN/`XLEN;
localparam integer lognumlines = $clog2(numlines); localparam integer lognumlines = $clog2(numlines);
localparam integer logblockbytelen = $clog2(blockbytelen); localparam integer loglinebytelen = $clog2(linebytelen);
localparam integer lognumways = $clog2(numways); localparam integer lognumways = $clog2(numways);
localparam integer tagstart = lognumlines + logblockbytelen; localparam integer tagstart = lognumlines + loglinebytelen;
@ -394,7 +380,7 @@ module DCacheFlushFSM
for(way = 0; way < numways; way++) begin for(way = 0; way < numways; way++) begin
for(cacheWord = 0; cacheWord < numwords; cacheWord++) begin for(cacheWord = 0; cacheWord < numwords; cacheWord++) begin
copyShadow #(.tagstart(tagstart), copyShadow #(.tagstart(tagstart),
.logblockbytelen(logblockbytelen)) .loglinebytelen(loglinebytelen))
copyShadow(.clk, copyShadow(.clk,
.start, .start,
.tag(testbench.dut.hart.lsu.dcache.dcache.MemWay[way].CacheTagMem.StoredData[index]), .tag(testbench.dut.hart.lsu.dcache.dcache.MemWay[way].CacheTagMem.StoredData[index]),
@ -431,19 +417,11 @@ module DCacheFlushFSM
end end
endgenerate flop #(1) doneReg(.clk, .d(start), .q(done));
flop #(1) doneReg(.clk(clk),
.d(start),
.q(done));
endmodule endmodule
module copyShadow module copyShadow
#(parameter tagstart, logblockbytelen) #(parameter tagstart, loglinebytelen)
(input logic clk, (input logic clk,
input logic start, input logic start,
input logic [`PA_BITS-1:tagstart] tag, input logic [`PA_BITS-1:tagstart] tag,
@ -464,7 +442,7 @@ module copyShadow
CacheValid = valid; CacheValid = valid;
CacheDirty = dirty; CacheDirty = dirty;
CacheData = data; CacheData = data;
CacheAdr = (tag << tagstart) + (index << logblockbytelen) + (cacheWord << $clog2(`XLEN/8)); CacheAdr = (tag << tagstart) + (index << loglinebytelen) + (cacheWord << $clog2(`XLEN/8));
end end
end end

5
pipelined/testbench/tests.vh
View File

@ -36,6 +36,7 @@ string tvpaths[] = '{
"../../tests/imperas-riscv-tests/work/" "../../tests/imperas-riscv-tests/work/"
}; };
// *** make sure these are somewhere
string imperas64a[] = '{ string imperas64a[] = '{
`MYIMPERASTEST, `MYIMPERASTEST,
"rv64a/WALLY-AMO", "2110", "rv64a/WALLY-AMO", "2110",
@ -48,7 +49,7 @@ string tvpaths[] = '{
"rv32a/WALLY-LRSC", "2110" "rv32a/WALLY-LRSC", "2110"
}; };
string imperas32mmu[] = '{ /* string imperas32mmu[] = '{
`MYIMPERASTEST, `MYIMPERASTEST,
"rv32mmu/WALLY-MMU-SV32", "3000", "rv32mmu/WALLY-MMU-SV32", "3000",
"rv32mmu/WALLY-PMP", "3000" "rv32mmu/WALLY-PMP", "3000"
@ -61,7 +62,7 @@ string tvpaths[] = '{
"rv64mmu/WALLY-MMU-SV39", "3000", "rv64mmu/WALLY-MMU-SV39", "3000",
"rv64mmu/WALLY-PMP", "3000" "rv64mmu/WALLY-PMP", "3000"
//"rv64mmu/WALLY-PMA", "3000" //"rv64mmu/WALLY-PMA", "3000"
}; }; */
// *** restore CSR tests from Imperas old // *** restore CSR tests from Imperas old