Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

.gitignore

@@ -10,4 +10,5 @@ wally-pipelined/wlft*
 wlft*
 /imperas-riscv-tests/FunctionRadix_32.addr
 /imperas-riscv-tests/FunctionRadix_64.addr
+/imperas-riscv-tests/FunctionRadix.addr
 /imperas-riscv-tests/ProgramMap.txt

wally-pipelined/src/ifu/ifu.sv

@@ -162,7 +162,7 @@ module ifu (
   endgenerate
 
   // Decode stage pipeline register and logic
-  flopenl #(32)    InstrDReg(clk, reset, ~StallD, (FlushD ? nop : InstrF), nop, InstrRawD);
+  flopenl #(32)    InstrDReg(clk, reset, ~StallD | FlushD, (FlushD ? nop : InstrF), nop, InstrRawD);
   flopenrc #(`XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD);
    
   // expand 16-bit compressed instructions to 32 bits

wally-pipelined/src/privileged/csri.sv

@@ -49,7 +49,7 @@ module csri #(parameter
   // assumes no N-mode user interrupts
 
   always_comb begin
-    IntInM     = 0;
+    IntInM     = 0; // *** does this really work
     IntInM[11] = ExtIntM & ~MIDELEG_REGW[9];   // MEIP
     IntInM[9]  = ExtIntM &  MIDELEG_REGW[9];   // SEIP
     IntInM[7]  = TimerIntM & ~MIDELEG_REGW[5]; // MTIP

wally-pipelined/src/privileged/privileged.sv

@@ -125,10 +125,10 @@ module privileged (
 
   // pipeline fault signals
   flopenrc #(1) faultregD(clk, reset, FlushD, ~StallD, InstrAccessFaultF, InstrAccessFaultD);
-  floprc #(2) faultregE(clk, reset, FlushE,
+  flopenrc #(2) faultregE(clk, reset, FlushE, ~StallE,
                            {IllegalIEUInstrFaultD, InstrAccessFaultD}, // ** vs IllegalInstrFaultInD
                            {IllegalIEUInstrFaultE, InstrAccessFaultE});
-  floprc #(2) faultregM(clk, reset, FlushM,
+  flopenrc #(2) faultregM(clk, reset, FlushM, ~StallM,
                          {IllegalIEUInstrFaultE, InstrAccessFaultE},
                          {IllegalIEUInstrFaultM, InstrAccessFaultM});
 

wally-pipelined/src/uncore/dtim.sv

@@ -85,15 +85,15 @@ module dtim #(parameter BASE=0, RANGE = 65535) (
   generate
     if (`XLEN == 64)  begin
       always_ff @(posedge HCLK) begin
-        HWADDR <= A;
-        HREADTim0 <= RAM[A[31:3]];
-        if (memwrite && risingHREADYTim) RAM[HWADDR[31:3]] <= HWDATA;
+        HWADDR <= #1 A;
+        HREADTim0 <= #1 RAM[A[31:3]];
+        if (memwrite && risingHREADYTim) RAM[HWADDR[31:3]] <= #1 HWDATA;
       end
     end else begin 
       always_ff @(posedge HCLK) begin
-        HWADDR <= A;  
-        HREADTim0 <= RAM[A[31:2]];
-        if (memwrite && risingHREADYTim) RAM[HWADDR[31:2]] <= HWDATA;
+        HWADDR <= #1 A;  
+        HREADTim0 <= #1 RAM[A[31:2]];
+        if (memwrite && risingHREADYTim) RAM[HWADDR[31:2]] <= #1 HWDATA;
       end
     end
   endgenerate

wally-pipelined/src/uncore/gpio.sv

@@ -33,6 +33,8 @@ module gpio (
   input  logic [7:0]       HADDR, 
   input  logic [`XLEN-1:0] HWDATA,
   input  logic             HWRITE,
+  input  logic             HREADY,
+  input  logic [1:0]       HTRANS,
   output logic [`XLEN-1:0] HREADGPIO,
   output logic             HRESPGPIO, HREADYGPIO,
   input  logic [31:0]      GPIOPinsIn,
@@ -40,15 +42,19 @@ module gpio (
 
   logic [31:0] INPUT_VAL, INPUT_EN, OUTPUT_EN, OUTPUT_VAL;
  
-  logic [7:0] entry;
-  logic            memread, memwrite;
+  logic [7:0] entry, HADDRd;
+  logic            initTrans, memread, memwrite;
 
-  assign memread  = HSELGPIO & ~HWRITE;
-  assign memwrite = HSELGPIO & HWRITE;
+  assign initTrans = HREADY & HSELGPIO & (HTRANS != 2'b00);
+
+  // Control Signals
+  flopenr #(1)  memreadreg(HCLK, ~HRESETn, initTrans, ~HWRITE, memread);
+  flopenr #(1) memwritereg(HCLK, ~HRESETn, initTrans, HWRITE, memwrite);
+  flopenr #(8)    haddrreg(HCLK, ~HRESETn, initTrans, HADDR, HADDRd);
+
+  // Response Signals
   assign HRESPGPIO = 0; // OK
-  always_ff @(posedge HCLK) // delay response to data cycle
-    HREADYGPIO <= memread | memwrite;
-//  assign HREADYGPIO = 1; // Respond immediately
+  assign HREADYGPIO = 1; // never ask for wait states
   
   // word aligned reads
   generate
@@ -103,7 +109,6 @@ module gpio (
         if (~HRESETn) begin
           INPUT_EN <= 0;
           OUTPUT_EN <= 0;
-          //OUTPUT_VAL <= 0;// spec indicates synchronous rset (software control)
         end else if (memwrite) begin
           if (entry == 8'h04) INPUT_EN <= HWDATA;
           if (entry == 8'h08) OUTPUT_EN <= HWDATA;