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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

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This commit is contained in:
Thomas Fleming 2021-03-25 02:35:21 -04:00
commit b5003b093a
6 changed files with 24 additions and 18 deletions
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1
.gitignore vendored
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@ -10,4 +10,5 @@ wally-pipelined/wlft*
wlft* wlft*
/imperas-riscv-tests/FunctionRadix_32.addr /imperas-riscv-tests/FunctionRadix_32.addr
/imperas-riscv-tests/FunctionRadix_64.addr /imperas-riscv-tests/FunctionRadix_64.addr
/imperas-riscv-tests/FunctionRadix.addr
/imperas-riscv-tests/ProgramMap.txt /imperas-riscv-tests/ProgramMap.txt

2
wally-pipelined/src/ifu/ifu.sv
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@ -162,7 +162,7 @@ module ifu (
endgenerate endgenerate
// Decode stage pipeline register and logic // Decode stage pipeline register and logic
flopenl #(32) InstrDReg(clk, reset, ~StallD, (FlushD ? nop : InstrF), nop, InstrRawD); flopenl #(32) InstrDReg(clk, reset, ~StallD | FlushD, (FlushD ? nop : InstrF), nop, InstrRawD);
flopenrc #(`XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD); flopenrc #(`XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD);
// expand 16-bit compressed instructions to 32 bits // expand 16-bit compressed instructions to 32 bits

2
wally-pipelined/src/privileged/csri.sv
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@ -49,7 +49,7 @@ module csri #(parameter
// assumes no N-mode user interrupts // assumes no N-mode user interrupts
always_comb begin always_comb begin
IntInM = 0; IntInM = 0; // *** does this really work
IntInM[11] = ExtIntM & ~MIDELEG_REGW[9]; // MEIP IntInM[11] = ExtIntM & ~MIDELEG_REGW[9]; // MEIP
IntInM[9] = ExtIntM & MIDELEG_REGW[9]; // SEIP IntInM[9] = ExtIntM & MIDELEG_REGW[9]; // SEIP
IntInM[7] = TimerIntM & ~MIDELEG_REGW[5]; // MTIP IntInM[7] = TimerIntM & ~MIDELEG_REGW[5]; // MTIP

4
wally-pipelined/src/privileged/privileged.sv
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@ -125,10 +125,10 @@ module privileged (
// pipeline fault signals // pipeline fault signals
flopenrc #(1) faultregD(clk, reset, FlushD, ~StallD, InstrAccessFaultF, InstrAccessFaultD); flopenrc #(1) faultregD(clk, reset, FlushD, ~StallD, InstrAccessFaultF, InstrAccessFaultD);
floprc #(2) faultregE(clk, reset, FlushE, flopenrc #(2) faultregE(clk, reset, FlushE, ~StallE,
{IllegalIEUInstrFaultD, InstrAccessFaultD}, // ** vs IllegalInstrFaultInD {IllegalIEUInstrFaultD, InstrAccessFaultD}, // ** vs IllegalInstrFaultInD
{IllegalIEUInstrFaultE, InstrAccessFaultE}); {IllegalIEUInstrFaultE, InstrAccessFaultE});
floprc #(2) faultregM(clk, reset, FlushM, flopenrc #(2) faultregM(clk, reset, FlushM, ~StallM,
{IllegalIEUInstrFaultE, InstrAccessFaultE}, {IllegalIEUInstrFaultE, InstrAccessFaultE},
{IllegalIEUInstrFaultM, InstrAccessFaultM}); {IllegalIEUInstrFaultM, InstrAccessFaultM});

12
wally-pipelined/src/uncore/dtim.sv
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@ -85,15 +85,15 @@ module dtim #(parameter BASE=0, RANGE = 65535) (
generate generate
if (`XLEN == 64) begin if (`XLEN == 64) begin
always_ff @(posedge HCLK) begin always_ff @(posedge HCLK) begin
HWADDR <= A; HWADDR <= #1 A;
HREADTim0 <= RAM[A[31:3]]; HREADTim0 <= #1 RAM[A[31:3]];
if (memwrite && risingHREADYTim) RAM[HWADDR[31:3]] <= HWDATA; if (memwrite && risingHREADYTim) RAM[HWADDR[31:3]] <= #1 HWDATA;
end end
end else begin end else begin
always_ff @(posedge HCLK) begin always_ff @(posedge HCLK) begin
HWADDR <= A; HWADDR <= #1 A;
HREADTim0 <= RAM[A[31:2]]; HREADTim0 <= #1 RAM[A[31:2]];
if (memwrite && risingHREADYTim) RAM[HWADDR[31:2]] <= HWDATA; if (memwrite && risingHREADYTim) RAM[HWADDR[31:2]] <= #1 HWDATA;
end end
end end
endgenerate endgenerate

21
wally-pipelined/src/uncore/gpio.sv
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@ -33,6 +33,8 @@ module gpio (
input logic [7:0] HADDR, input logic [7:0] HADDR,
input logic [`XLEN-1:0] HWDATA, input logic [`XLEN-1:0] HWDATA,
input logic HWRITE, input logic HWRITE,
input logic HREADY,
input logic [1:0] HTRANS,
output logic [`XLEN-1:0] HREADGPIO, output logic [`XLEN-1:0] HREADGPIO,
output logic HRESPGPIO, HREADYGPIO, output logic HRESPGPIO, HREADYGPIO,
input logic [31:0] GPIOPinsIn, input logic [31:0] GPIOPinsIn,
@ -40,15 +42,19 @@ module gpio (
logic [31:0] INPUT_VAL, INPUT_EN, OUTPUT_EN, OUTPUT_VAL; logic [31:0] INPUT_VAL, INPUT_EN, OUTPUT_EN, OUTPUT_VAL;
logic [7:0] entry; logic [7:0] entry, HADDRd;
logic memread, memwrite; logic initTrans, memread, memwrite;
assign memread = HSELGPIO & ~HWRITE; assign initTrans = HREADY & HSELGPIO & (HTRANS != 2'b00);
assign memwrite = HSELGPIO & HWRITE;
// Control Signals
flopenr #(1) memreadreg(HCLK, ~HRESETn, initTrans, ~HWRITE, memread);
flopenr #(1) memwritereg(HCLK, ~HRESETn, initTrans, HWRITE, memwrite);
flopenr #(8) haddrreg(HCLK, ~HRESETn, initTrans, HADDR, HADDRd);
// Response Signals
assign HRESPGPIO = 0; // OK assign HRESPGPIO = 0; // OK
always_ff @(posedge HCLK) // delay response to data cycle assign HREADYGPIO = 1; // never ask for wait states
HREADYGPIO <= memread | memwrite;
// assign HREADYGPIO = 1; // Respond immediately
// word aligned reads // word aligned reads
generate generate
@ -103,7 +109,6 @@ module gpio (
if (~HRESETn) begin if (~HRESETn) begin
INPUT_EN <= 0; INPUT_EN <= 0;
OUTPUT_EN <= 0; OUTPUT_EN <= 0;
//OUTPUT_VAL <= 0;// spec indicates synchronous rset (software control)
end else if (memwrite) begin end else if (memwrite) begin
if (entry == 8'h04) INPUT_EN <= HWDATA; if (entry == 8'h04) INPUT_EN <= HWDATA;
if (entry == 8'h08) OUTPUT_EN <= HWDATA; if (entry == 8'h08) OUTPUT_EN <= HWDATA;