mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge pull request #776 from davidharrishmc/dev
Added -H to pip3 installation to install in system home directory
This commit is contained in:
Rose Thompson
GitHub
commit
b4fc47cd65
5
.gitignore
vendored
5
.gitignore
vendored
@ -229,4 +229,7 @@ examples/verilog/fulladder/profileReport/
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examples/verilog/fulladder/simprofile_dir/
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examples/verilog/fulladder/simv.daidir/
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examples/verilog/fulladder/ucli.key
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examples/verilog/fulladder/verdi_config_file
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examples/verilog/fulladder/verdi_config_file
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tests/functcov
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tests/functcov/*
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tests/functcov/*/*
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@ -48,7 +48,7 @@ sudo apt update -y
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sudo apt upgrade -y
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sudo apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev python3-pip pkg-config opam z3 zlib1g-dev automake autotools-dev libmpc-dev libmpfr-dev gperf libtool patchutils bc mutt ssmtp
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# Other python libraries used through the book.
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sudo pip3 install sphinx sphinx_rtd_theme matplotlib scipy scikit-learn adjustText lief markdown
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sudo -H pip3 install sphinx sphinx_rtd_theme matplotlib scipy scikit-learn adjustText lief markdown
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# needed for Ubuntu 22.04, gcc cross compiler expects python not python2 or python3.
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if ! command -v python &> /dev/null
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@ -183,8 +183,8 @@ sudo ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 /usr/bin/riscv_sim_RV64
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sudo ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32
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# riscof
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sudo pip3 install -U testresources riscv_config
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sudo pip3 install git+https://github.com/riscv/riscof.git
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sudo -H pip3 install -U testresources riscv_config
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sudo -H pip3 install git+https://github.com/riscv/riscof.git
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# Download OSU Skywater 130 cell library
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sudo mkdir -p $RISCV/cad/lib
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@ -1,4 +1,39 @@
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all:
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#all:
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# ./covergen.py
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# cd ../riscof; make wally-riscv-arch-test
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# cd ../../sim; make memfiles
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CEXT := c
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CPPEXT := cpp
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AEXT := s
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SEXT := S
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SRCEXT := \([$(CEXT)$(AEXT)$(SEXT)]\|$(CPPEXT)\)
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#SRCS = $(wildcard *.S)
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#PROGS = $(patsubst %.S,%,$(SRCS))
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SRCDIR = ${WALLY}/tests/functcov/rv64/I
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SRCEXT = S
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SOURCES ?= $(shell find $(SRCDIR) -type f -regex ".*\.$(SRCEXT)" | sort)
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OBJEXT = elf
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OBJECTS := $(SOURCES:.$(SEXT)=.$(OBJEXT))
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all:
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./covergen.py
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cd ../riscof; make wally-riscv-arch-test
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cd ../../sim; make memfiles
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make build
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build: $(OBJECTS)
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%.elf.objdump: %.elf
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# Change many things if bit width isn't 64
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$(SRCDIR)/%.elf: $(SRCDIR)/%.$(SEXT)
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riscv64-unknown-elf-gcc -g -o $@ -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom -mabi=lp64 -mcmodel=medany \
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-nostartfiles -T${WALLY}/examples/link/link.ld $<
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riscv64-unknown-elf-objdump -S -D $@ > $@.objdump
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riscv64-unknown-elf-elf2hex --bit-width 64 --input $@ --output $@.memfile
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extractFunctionRadix.sh $@.objdump
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clean:
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rm -f ${SRCDIR}/*.elf ${SRCDIR}/*.objdump ${SRCDIR}/*.addr *${SRCDIR}/.lab ${SRCDIR}/*.memfile
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@ -14,7 +14,7 @@ from datetime import datetime
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from random import randint
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from random import seed
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from random import getrandbits
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from os import getenv
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import os
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import re
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##################################
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@ -33,16 +33,16 @@ def signedImm12(imm):
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def writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, storecmd, xlen):
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lines = "\n# Testcase " + str(desc) + "\n"
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lines = lines + "li x" + str(rd) + ", MASK_XLEN(" + formatstr.format(rdval) + ") # initialize rd to a random value that should get changed\n"
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lines = lines + "li x" + str(rd) + ", " + formatstr.format(rdval) + " # initialize rd to a random value that should get changed\n"
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if (test in rtype):
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lines = lines + "li x" + str(rs1) + ", MASK_XLEN(" + formatstr.format(rs1val) + ") # initialize rs1 to a random value \n"
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lines = lines + "li x" + str(rs2) + ", MASK_XLEN(" + formatstr.format(rs2val) + ") # initialize rs2 to a random value\n"
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lines = lines + "li x" + str(rs1) + ", " + formatstr.format(rs1val) + " # initialize rs1 to a random value \n"
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lines = lines + "li x" + str(rs2) + ", " + formatstr.format(rs2val) + " # initialize rs2 to a random value\n"
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lines = lines + test + " x" + str(rd) + ", x" + str(rs1) + ", x" + str(rs2) + " # perform operation\n"
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elif (test in shiftitype):
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lines = lines + "li x" + str(rs1) + ", MASK_XLEN(" + formatstr.format(rs1val) + ") # initialize rs1 to a random value \n"
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lines = lines + "li x" + str(rs1) + ", " + formatstr.format(rs1val) + " # initialize rs1 to a random value \n"
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lines = lines + test + " x" + str(rd) + ", x" + str(rs1) + ", " + shiftImm(immval, xlen) + " # perform operation\n"
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elif (test in itype):
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lines = lines + "li x" + str(rs1) + ", MASK_XLEN(" + formatstr.format(rs1val) + ") # initialize rs1 to a random value \n"
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lines = lines + "li x" + str(rs1) + ", " + formatstr.format(rs1val) + " # initialize rs1 to a random value \n"
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lines = lines + test + " x" + str(rd) + ", x" + str(rs1) + ", " + signedImm12(immval) + " # perform operation\n"
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else:
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pass
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@ -79,22 +79,28 @@ def make_rs2(test, storecmd, xlen):
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def make_rd_rs1(test, storecmd, xlen):
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for r in range(32):
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[rs1, rs1, rd, rs1val, rs2val, immval, rdval] = randomize()
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[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
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desc = "cp_rd_rs1 (Test rd = rs1 = x" + str(r) + ")"
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writeCovVector(desc, r, rs2, r, rs1val, rs2val, immval, rdval, test, storecmd, xlen)
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def make_rd_rs2(test, storecmd, xlen):
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for r in range(32):
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[rs1, rs1, rd, rs1val, rs2val, immval, rdval] = randomize()
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[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
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desc = "cp_rd_rs2 (Test rd = rs1 = x" + str(r) + ")"
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writeCovVector(desc, rs1, r, r, rs1val, rs2val, immval, rdval, test, storecmd, xlen)
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def make_rd_rs1_rs2(test, storecmd, xlen):
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for r in range(32):
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[rs1, rs1, rd, rs1val, rs2val, immval, rdval] = randomize()
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[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
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desc = "cp_rd_rs1_rs2 (Test rd = rs1 = rs2 = x" + str(r) + ")"
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writeCovVector(desc, r, r, r, rs1val, rs2val, immval, rdval, test, storecmd, xlen)
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def make_rs1_rs2(test, storecmd, xlen):
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for r in range(32):
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[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
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desc = "cp_rd_rs1_rs2 (Test rs1 = rs2 = x" + str(r) + ")"
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writeCovVector(desc, r, r, rd, rs1val, rs2val, immval, rdval, test, storecmd, xlen)
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def make_rs1_maxvals(test, storecmd, xlen):
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for v in [0, 2**(xlen-1), 2**(xlen-1)-1, 2**xlen-1, 1, 2**(xlen-1)+1]:
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[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
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@ -131,6 +137,29 @@ def make_rs1_rs2_eqval(test, storecmd, xlen):
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#def make_cp_gpr_hazard(test, storecmd, xlen):
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# pass # *** to be implemented ***
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def make_rs1_sign(test, storecmd, xlen):
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for v in [1, -1]:
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[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
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rs1val = abs(rs1val) * v;
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desc = "cp_rs1_sign (Test source rs1 value = " + hex(rs1val) + ")"
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writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, storecmd, xlen)
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def make_rs2_sign(test, storecmd, xlen):
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for v in [1, -1]:
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[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
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rs2val = abs(rs2val) * v;
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desc = "cp_rs2_sign (Test source rs2 value = " + hex(rs2val) + ")"
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writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, storecmd, xlen)
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def make_cr_rs1_rs2_sign(test, storecmd, xlen):
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for v1 in [1, -1]:
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for v2 in [1, -1]:
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[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
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rs1val = abs(rs1val) * v1;
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rs2val = abs(rs2val) * v2;
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desc = "cr_rs1_rs2 (Test source rs1 = " + hex(rs1val) + " rs2 = " + hex(rs2val) + ")"
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writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, storecmd, xlen)
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def write_tests(coverpoints, test, storecmd, xlen):
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for coverpoint in coverpoints:
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if (coverpoint == "cp_asm_count"):
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@ -141,12 +170,18 @@ def write_tests(coverpoints, test, storecmd, xlen):
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make_rs1(test, storecmd, xlen)
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elif (coverpoint == "cp_rs2"):
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make_rs2(test, storecmd, xlen)
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elif (coverpoint == "cp_rd_rs1"):
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elif (coverpoint == "cmp_rd_rs1"):
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make_rd_rs1(test, storecmd, xlen)
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elif (coverpoint == "cp_rd_rs2"):
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elif (coverpoint == "cmp_rd_rs2"):
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make_rd_rs2(test, storecmd, xlen)
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elif (coverpoint == "cp_rd_rs1_rs2"):
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elif (coverpoint == "cmp_rd_rs1_rs2"):
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make_rd_rs1_rs2(test, storecmd, xlen)
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elif (coverpoint == "cmp_rd_rs1_eq"):
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pass # duplicate of cmp_rd_rs1
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elif (coverpoint == "cmp_rd_rs2_eq"):
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pass # duplicate of cmp_rd_rs2
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elif (coverpoint == "cmp_rs1_rs2_eq"):
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make_rs1_rs2(test, storecmd, xlen)
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elif (coverpoint == "cp_rs1_maxvals"):
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make_rs1_maxvals(test, storecmd, xlen)
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elif (coverpoint == "cp_rs2_maxvals"):
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@ -159,8 +194,22 @@ def write_tests(coverpoints, test, storecmd, xlen):
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make_rd_rs2_eqval(test, storecmd, xlen)
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elif (coverpoint == "cmp_rs1_rs2_eqval"):
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make_rs1_rs2_eqval(test, storecmd, xlen)
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# elif (coverpoint == "cp_gpr_hazard"):
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# make_cp_gpr_hazard(test, storecmd, xlen)
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elif (coverpoint == "cp_rs1_sign"):
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make_rs1_sign(test, storecmd, xlen)
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elif (coverpoint == "cp_rs2_sign"):
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make_rs2_sign(test, storecmd, xlen)
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elif (coverpoint == "cp_rd_sign"):
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pass # hope already covered by rd_maxvals
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elif (coverpoint == "cr_rs1_rs2"):
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make_cr_rs1_rs2_sign(test, storecmd, xlen)
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elif (coverpoint == "cp_rs1_toggle"):
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pass # toggle not needed and seems to be covered by other things
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elif (coverpoint == "cp_rs2_toggle"):
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pass # toggle not needed and seems to be covered by other things
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elif (coverpoint == "cp_rd_toggle"):
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pass # toggle not needed and seems to be covered by other things
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elif (coverpoint == "cp_gpr_hazard"):
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pass # not yet implemented
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else:
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print("Error: " + coverpoint + " not implemented yet for " + test)
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@ -188,7 +237,7 @@ def getcovergroups(coverdefdir, coverfiles):
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##################################
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# change these to suite your tests
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riscv = getenv("RISCV")
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riscv = os.environ.get("RISCV")
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coverdefdir = riscv+"/ImperasDV-OpenHW/Imperas/ImpProprietary/source/host/riscvISACOV/source/coverage";
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#coverfiles = ["RV64I", "RV64M", "RV64A", "RV64C", "RV64F", "RV64D"] # add more later
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coverfiles = ["RV64I"] # add more later
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@ -222,13 +271,13 @@ for xlen in xlens:
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storecmd = "sd"
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wordsize = 8
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for test in coverpoints.keys():
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# for test in tests:
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# corners = [0, 1, 2, 0xFF, 0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1,
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# 2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1]
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corners = [0, 1, 2**(xlen)-1]
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pathname = "../wally-riscv-arch-test/riscv-test-suite/rv" + str(xlen) + "i_m/I/"
|
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# pathname = "../wally-riscv-arch-test/riscv-test-suite/rv" + str(xlen) + "i_m/I/"
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WALLY = os.environ.get('WALLY')
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pathname = WALLY+"/tests/functcov/rv" + str(xlen) + "/I/"
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cmd = "mkdir -p " + pathname
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os.system(cmd)
|
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basename = "WALLY-COV-" + test
|
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fname = pathname + "src/" + basename + ".S"
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fname = pathname + "/" + basename + ".S"
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# print custom header part
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f = open(fname, "w")
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|
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@ -1,30 +1,2 @@
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RVTEST_CODE_END
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RVMODEL_HALT
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|
||||
RVTEST_DATA_BEGIN
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.align 4
|
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rvtest_data:
|
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.word 0x98765432
|
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RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
|
||||
|
||||
wally_signature:
|
||||
.fill NUMTESTS*(XLEN/32),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*(XLEN/32),4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*(XLEN/32),4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
RVMODEL_DATA_END
|
||||
.end
|
||||
|
||||
@ -4,18 +4,9 @@
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
///////////////////////////////////////////
|
||||
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV64I")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",temp)
|
||||
|
||||
la x6, wally_signature
|
||||
sd x0, 0(x6)
|
||||
|
||||
@ -1,292 +0,0 @@
|
||||
#!/usr/bin/python3
|
||||
##################################
|
||||
# virtual_memory_util.py
|
||||
#
|
||||
# Jessica Torrey <jtorrey@hmc.edu> 01 March 2021
|
||||
# Thomas Fleming <tfleming@hmc.edu> 01 March 2021
|
||||
#
|
||||
# Modified kmacsaigoren@hmc.edu 2 June 2021
|
||||
# file now reflects actual use to generate assembly code pagetable.
|
||||
# file now also includes small guide on how it can be used.
|
||||
#
|
||||
# Utility for generating the pagetable for any test assembly code where virtual memory is needed.
|
||||
##################################
|
||||
|
||||
######################################################
|
||||
""" HOW TO USE THIS FILE
|
||||
|
||||
This is all assuming you are writing code very similar to the WALLY-VIRTUALMEMORY tests and would like your own virtual memory map.
|
||||
This guide is also stored in the WALLY-VIRTUALMEMORY.S file as well.
|
||||
|
||||
Begin by copying an existing page directory over to your test and running make (it'll be wrong, but we'll fix it in a second).
|
||||
Make may hang or give you an error because the reference outputs may be wrong, but all we're trying to do is get an elf file.
|
||||
Simulate the test code on your favorite riscv processor simulator with a debugger that will show you internal state/register values.
|
||||
I used OVPsimPlus with the command 'riscvOVPsimPlus.exe --variant <Variant name, ex: RV64I> --program <path to elf file> --gdbconsole'
|
||||
Run through the simulation until it has written to satp and read the bottom 60 bits of it.
|
||||
Assuming you're a test with the same setup code, this should be the value of the base ppn.
|
||||
|
||||
Near the top of the python file you're reading right now, edit the value of 'INITIAL_PPN' to be the base PPN you just found in hex.
|
||||
|
||||
Now find the mappings at the very bottom of the python file.
|
||||
Each of these loops is adding a mapping from each virtual page in the loop to a physical page somewhere in RAM.
|
||||
|
||||
add or remove mappings as you see fit. the first loop maps VPNs of 0x80000 to 0x80014 onto PPNs of 0x80000 to 0x80014
|
||||
you can map single pages or ranges of pages. you can also map multiple VPNs onto the same PPN.
|
||||
Make sure NOT to include the final VPN that causes the page fault in your test or your program will hang on the j loop instruction (unless you change the end condition).
|
||||
|
||||
double check that you're using the right architecture/svmode in the 'arch' variable
|
||||
|
||||
then run this python file and paste its output at the bottom of your assembly code. Be sure not to delete the signature fills.
|
||||
|
||||
email kmacsaigoren@hmc.edu if you have any questions and he might be able to remember the answers.
|
||||
|
||||
*** Currently doesn't work: mapping something with nonzeros in the VPN[3] feild onto any physical aderss.
|
||||
It'll produce a page table, but writing to those virtual adresses will not correspond to the correctly mapped physical adresses.
|
||||
|
||||
additionally, the expected behaviour doesn't really work when we try to map to a ram afress that starts with something larger than 000000008
|
||||
This could be ebcause of the 32 bit adress space for physical memory.
|
||||
|
||||
remember that these things are broken with this program that generates page tables for test code. it does not say whether the test or module
|
||||
itself works or not.
|
||||
*/
|
||||
|
||||
"""
|
||||
######################################################
|
||||
|
||||
##################################
|
||||
# libraries
|
||||
##################################
|
||||
from datetime import datetime
|
||||
from random import randint, seed, getrandbits
|
||||
from textwrap import dedent
|
||||
|
||||
##################################
|
||||
# global structures
|
||||
##################################
|
||||
PTE_D = 1 << 7
|
||||
PTE_A = 1 << 6
|
||||
PTE_G = 1 << 5
|
||||
PTE_U = 1 << 4
|
||||
PTE_X = 1 << 3
|
||||
PTE_W = 1 << 2
|
||||
PTE_R = 1 << 1
|
||||
PTE_V = 1 << 0
|
||||
|
||||
PTE_PTR_MASK = ~(PTE_W | PTE_R | PTE_X)
|
||||
|
||||
pgdir = []
|
||||
|
||||
pages = {}
|
||||
|
||||
|
||||
testcase_num = 0
|
||||
signature_len = 2000
|
||||
signature = [0xff for _ in range(signature_len)]
|
||||
|
||||
# Base PPN, comes after 2 pages of test code and 2 pages of filler signature output space.
|
||||
# depending on your test however, this value may be different. You can use OVPsimPlus or QEMU with your testcode to find it.
|
||||
INITIAL_PPN = 0x80005
|
||||
|
||||
|
||||
##################################
|
||||
# classes
|
||||
##################################
|
||||
class Architecture:
|
||||
def __init__(self, xlen, svMode):
|
||||
if (xlen == 32):
|
||||
self.PTESIZE = 4 # bytes
|
||||
self.PTE_BITS = 32
|
||||
|
||||
self.VPN_BITS = 20
|
||||
self.VPN_SEGMENT_BITS = 10
|
||||
|
||||
self.PPN_BITS = 22
|
||||
|
||||
self.LEVELS = 2
|
||||
elif (xlen == 64):
|
||||
if (svMode == 39):
|
||||
self.PTESIZE = 8
|
||||
self.PTE_BITS = 54
|
||||
|
||||
self.VPN_BITS = 27
|
||||
self.VPN_SEGMENT_BITS = 9
|
||||
|
||||
self.PPN_BITS = 44
|
||||
|
||||
self.LEVELS = 3
|
||||
elif (svMode == 48):
|
||||
self.PTESIZE = 8
|
||||
self.PTE_BITS = 54
|
||||
|
||||
self.VPN_BITS = 36
|
||||
self.VPN_SEGMENT_BITS = 9
|
||||
|
||||
self.PPN_BITS = 44
|
||||
|
||||
self.LEVELS = 4
|
||||
else:
|
||||
raise ValueError('Only Sv39 and Sv48 are implemented')
|
||||
else:
|
||||
raise ValueError('Only rv32 and rv64 are allowed.')
|
||||
|
||||
self.PGSIZE = 2**12
|
||||
self.NPTENTRIES = self.PGSIZE // self.PTESIZE
|
||||
self.OFFSET_BITS = 12
|
||||
self.FLAG_BITS = 8
|
||||
self.VA_BITS = self.VPN_BITS + self.OFFSET_BITS
|
||||
|
||||
class PageTableEntry:
|
||||
def __init__(self, ppn, flags, arch):
|
||||
assert 0 <= ppn and ppn < 2**arch.PPN_BITS, "Invalid physical page number for PTE"
|
||||
assert 0 <= flags and flags < 2**arch.FLAG_BITS, "Invalid flags for PTE"
|
||||
self.ppn = ppn
|
||||
self.flags = flags
|
||||
self.arch = arch
|
||||
|
||||
def entry(self):
|
||||
return (self.ppn << (self.arch.PTE_BITS - self.arch.PPN_BITS)) | self.flags
|
||||
|
||||
def __str__(self):
|
||||
return "0x{0:0{1}x}".format(self.entry(), self.arch.PTESIZE*2)
|
||||
|
||||
def __repr__(self):
|
||||
return f"<ppn: {hex(self.ppn)}, flags: {self.flags:08b}>"
|
||||
|
||||
class PageTable:
|
||||
"""
|
||||
Represents a single level of the page table, located at some physical page
|
||||
number `ppn` with symbol `name`, using a specified architecture `arch`.
|
||||
"""
|
||||
def __init__(self, name, ppn, arch):
|
||||
self.table = {}
|
||||
self.name = name
|
||||
self.ppn = ppn
|
||||
self.arch = arch
|
||||
|
||||
self.children = 0
|
||||
|
||||
pages[ppn] = self
|
||||
|
||||
def add_entry(self, vpn_segment, ppn, flags):
|
||||
if not (0 <= vpn_segment < 2**self.arch.VPN_SEGMENT_BITS):
|
||||
raise ValueError("Invalid virtual page segment number")
|
||||
self.table[vpn_segment] = PageTableEntry(ppn, flags, self.arch)
|
||||
|
||||
def add_mapping(self, va, pa, flags):
|
||||
"""
|
||||
Maps a virtual address `va` to a physical address `pa` with given `flags`,
|
||||
creating missing page table levels as needed.
|
||||
"""
|
||||
if not (0 <= va < 2**self.arch.VA_BITS):
|
||||
raise ValueError("Invalid virtual page number")
|
||||
|
||||
vpn = virtual_to_vpn(va, self.arch)
|
||||
ppn = pa >> self.arch.OFFSET_BITS
|
||||
current_level = self
|
||||
|
||||
pathname = self.name
|
||||
|
||||
for level in range(self.arch.LEVELS - 1, -1, -1):
|
||||
if level == 0:
|
||||
current_level.add_entry(vpn[level], ppn, flags)
|
||||
elif vpn[level] in current_level.table:
|
||||
current_level = pages[current_level.table[vpn[level]].ppn]
|
||||
pathname += f"_{current_level.name}"
|
||||
else:
|
||||
next_level_ppn = next_ppn()
|
||||
current_level.add_entry(vpn[level], next_level_ppn, flags & PTE_PTR_MASK)
|
||||
pathname += f"_t{current_level.children}"
|
||||
current_level.children += 1
|
||||
pages[next_level_ppn] = PageTable(pathname, next_level_ppn, self.arch)
|
||||
current_level = pages[next_level_ppn]
|
||||
|
||||
def assembly(self):
|
||||
# Sort the page table
|
||||
entries = list(sorted(self.table.items(), key=lambda item: item[0]))
|
||||
current_index = 0
|
||||
|
||||
# Align the table
|
||||
asm = f".balign {self.arch.PGSIZE}\n{self.name}:\n"
|
||||
for entry in entries:
|
||||
vpn_index, pte = entry
|
||||
if current_index < vpn_index:
|
||||
asm += f" .fill {vpn_index - current_index}, {self.arch.PTESIZE}, 0\n"
|
||||
asm += f" .{self.arch.PTESIZE}byte {str(pte)}\n"
|
||||
current_index = vpn_index + 1
|
||||
if current_index < self.arch.NPTENTRIES:
|
||||
asm += f" .fill {self.arch.NPTENTRIES - current_index}, {self.arch.PTESIZE}, 0\n"
|
||||
return asm
|
||||
|
||||
def __str__(self):
|
||||
return self.assembly()
|
||||
|
||||
def __repr__(self):
|
||||
return f"<table: {self.table}>"
|
||||
|
||||
|
||||
##################################
|
||||
# functions
|
||||
##################################
|
||||
|
||||
def virtual_to_vpn(vaddr, arch):
|
||||
if not (0 <= vaddr < 2**arch.VA_BITS):
|
||||
raise ValueError("Invalid physical address")
|
||||
|
||||
page_number = [0 for _ in range(arch.LEVELS)]
|
||||
|
||||
vaddr = vaddr >> arch.OFFSET_BITS
|
||||
mask = 2**arch.VPN_SEGMENT_BITS - 1
|
||||
for level in range(arch.LEVELS):
|
||||
page_number[level] = vaddr & mask
|
||||
vaddr = vaddr >> arch.VPN_SEGMENT_BITS
|
||||
|
||||
return page_number
|
||||
|
||||
next_free_ppn = INITIAL_PPN
|
||||
def next_ppn():
|
||||
global next_free_ppn
|
||||
ppn = next_free_ppn
|
||||
next_free_ppn += 1
|
||||
return ppn
|
||||
|
||||
def print_pages():
|
||||
for page in pages:
|
||||
print(pages[page])
|
||||
|
||||
##################################
|
||||
# helper variables
|
||||
##################################
|
||||
sv32 = Architecture(32, 32)
|
||||
sv39 = Architecture(64, 39)
|
||||
sv48 = Architecture(64, 48)
|
||||
|
||||
if __name__ == "__main__":
|
||||
arch = sv39
|
||||
pgdir = PageTable("page_directory", next_ppn(), arch)
|
||||
|
||||
# Directly map the first 20 pages of RAM
|
||||
for page in range(20):
|
||||
vaddr = 0x80000000 + (arch.PGSIZE * page)
|
||||
paddr = 0x80000000 + (arch.PGSIZE * page)
|
||||
pgdir.add_mapping(vaddr, paddr, PTE_D | PTE_A | PTE_R | PTE_W | PTE_U | PTE_X | PTE_V)
|
||||
|
||||
# Map Vpn of of the offset below and the 20 pages after it mapped onto the same 20 pages of ram.
|
||||
# the first two of these are also the location of the output for each test.
|
||||
for page in range(40):
|
||||
vaddr = 0x00000000 + (arch.PGSIZE * page)
|
||||
paddr = 0x80000000 + (arch.PGSIZE * page)
|
||||
if page >= 20:
|
||||
pgdir.add_mapping(vaddr, paddr, PTE_D | PTE_A | PTE_R | PTE_W | PTE_U | PTE_X | 0) # gives me an invalid mapping where I can try to store/read to force a page fault.
|
||||
else:
|
||||
pgdir.add_mapping(vaddr, paddr, PTE_D | PTE_A | PTE_R | PTE_W | PTE_U | PTE_X | PTE_V)
|
||||
|
||||
|
||||
"""
|
||||
supervisor_pgdir = PageTable("sdir", next_ppn(), rv64)
|
||||
supervisor_pgdir.add_mapping(0x80000000, 0x80000000, PTE_R | PTE_W | PTE_X)
|
||||
supervisor_pgdir.add_mapping(0x80000001, 0x80000001, PTE_R | PTE_W | PTE_X)
|
||||
supervisor_pgdir.add_mapping(0x80001000, 0x80000000, PTE_R | PTE_W | PTE_X)
|
||||
supervisor_pgdir.add_mapping(0xffff0000, 0x80000000, PTE_R | PTE_W | PTE_X)
|
||||
"""
|
||||
|
||||
print_pages()
|
||||
Loading…
Reference in New Issue
Block a user