From b4bdf446ccef6989e1ea6fe9297629937efff154 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 20 Dec 2022 17:34:11 -0600 Subject: [PATCH] Implement FENCE.I as NOP when ZIFENCEI is not supported. --- pipelined/src/ieu/controller.sv | 6 +++++- pipelined/src/ifu/ifu.sv | 4 ++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/pipelined/src/ieu/controller.sv b/pipelined/src/ieu/controller.sv index d1aa1b8ed..1565656ce 100644 --- a/pipelined/src/ieu/controller.sv +++ b/pipelined/src/ieu/controller.sv @@ -127,7 +127,10 @@ module controller( 7'b0000000: ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // illegal instruction 7'b0000011: ControlsD = `CTRLW'b1_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0; // lw 7'b0000111: ControlsD = `CTRLW'b0_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0; // flw - only legal if FP supported - 7'b0001111: ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_1_0_00_0; // fence + 7'b0001111: if(`ZIFENCEI_SUPPORTED) + ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_1_0_00_0; // fence + else + ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_0; // fence 7'b0010011: ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_0_0_0_0_0_00_0; // I-type ALU 7'b0010111: ControlsD = `CTRLW'b1_100_11_00_000_0_0_0_0_0_0_0_0_0_00_0; // auipc 7'b0011011: if (`XLEN == 64) @@ -180,6 +183,7 @@ module controller( assign {RegWriteD, ImmSrcD, ALUSrcAD, ALUSrcBD, MemRWD, ResultSrcD, BranchD, ALUOpD, JumpD, ALUResultSrcD, W64D, CSRReadD, PrivilegedD, FenceXD, MDUD, AtomicD, unused} = IllegalIEUInstrFaultD ? `CTRLW'b0 : ControlsD; + assign CSRZeroSrcD = InstrD[14] ? (InstrD[19:15] == 0) : (Rs1D == 0); // Is a CSR instruction using zero as the source? assign CSRWriteD = CSRReadD & !(CSRZeroSrcD & InstrD[13]); // Don't write if setting or clearing zeros diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 427e9038e..7f1f10f35 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -285,10 +285,10 @@ module ifu ( // PCNextF logic //////////////////////////////////////////////////////////////////////////////////////////////// -// if(`ICACHE | `ZICSR_SUPPORTED) + if(`ICACHE | `ZIFENCEI_SUPPORTED) mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(NextValidPCE), .s(CSRWriteFenceM),.y(PCNext2F)); // mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(PCM+4), .s(CSRWriteFenceM),.y(PCNext2F)); -// else assign PCNext2F = PCNext1F; + else assign PCNext2F = PCNext1F; if(`ZICSR_SUPPORTED) begin logic PrivilegedChangePCM; assign PrivilegedChangePCM = RetM | TrapM;