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Merge pull request #926 from ross144/main

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Fix my name on multiple files and other minor changes
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David Harris 2024-08-22 03:23:17 -07:00 committed by GitHub
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42 changed files with 46 additions and 62 deletions
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2
addins/cvw-arch-verif

@ -1 +1 @@
Subproject commit 07679a31750eb1054055afff0d42f467c5e87727 Subproject commit 9d54f3f8e902bb85db74305993d2fc03796b57bc

2
bin/extractFunctionRadix.sh
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@ -3,7 +3,7 @@
###################### ######################
## extractFunctionRadix.sh ## extractFunctionRadix.sh
## ##
## Written: Ross Thompson ## Written: Rose Thompson
## email: ross1728@gmail.com ## email: ross1728@gmail.com
## Created: March 1, 2021 ## Created: March 1, 2021
## Modified: March 10, 2021 ## Modified: March 10, 2021

2
bin/wally-tool-chain-install.sh
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@ -2,7 +2,7 @@
########################################### ###########################################
## Tool chain install script. ## Tool chain install script.
## ##
## Written: Ross Thompson ross1728@gmail.com ## Written: Rose Thompson ross1728@gmail.com
## Created: 18 January 2023 ## Created: 18 January 2023
## Modified: 22 January 2023 ## Modified: 22 January 2023
## Modified: 23 March 2023 ## Modified: 23 March 2023

2
fpga/comport.setup
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@ -1,3 +1,3 @@
sudo chown ross:ross /dev/ttyUSB1 sudo chown rose:rose /dev/ttyUSB1
stty -F /dev/ttyUSB1 57600 cs8 -cstopb -parenb stty -F /dev/ttyUSB1 57600 cs8 -cstopb -parenb
cat /dev/ttyUSB1 cat /dev/ttyUSB1

2
fpga/src/wallypipelinedsocwrapper.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// wallypipelinedsocwrapper.sv // wallypipelinedsocwrapper.sv
// //
// Written: Ross Thompson ross1728@gmail.com 16 June 2023 // Written: Rose Thompson ross1728@gmail.com 16 June 2023
// Modified: // Modified:
// //
// Purpose: A wrapper to set parameters. Vivado cannot set the top level parameters because it only supports verilog, // Purpose: A wrapper to set parameters. Vivado cannot set the top level parameters because it only supports verilog,

2
linux/testvector-generation/parseGDBtoTrace.py
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@ -1,7 +1,7 @@
#!/usr/bin/env python3 #!/usr/bin/env python3
import sys, fileinput, re import sys, fileinput, re
# Ross Thompson # Rose Thompson
# July 27, 2021 # July 27, 2021
# Rewrite of the linux trace parser. # Rewrite of the linux trace parser.

4
sim/Makefile
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@ -30,8 +30,8 @@ QuestaCodeCoverage: questa/ucdb/rv64gc_arch64i.ucdb
# vcover report -recursive questa/ucdb/cov.ucdb > questa/cov/rv64gc_recursive.rpt # vcover report -recursive questa/ucdb/cov.ucdb > questa/cov/rv64gc_recursive.rpt
vcover report -details -threshH 100 -html questa/ucdb/cov.ucdb vcover report -details -threshH 100 -html questa/ucdb/cov.ucdb
QuestaFunctCoverage: ${SIM}/questa/fcov_ucdb/rv64gc_WALLY-COV-add.elf.ucdb QuestaFunctCoverage: ${SIM}/questa/fcov_ucdb/rv64gc_I_WALLY-COV-add.elf.ucdb
vcover merge -out ${SIM}/questa/fcov_ucdb/fcov.ucdb ${SIM}/questa/fcov_ucdb/rv64gc_WALLY-COV-add.elf.ucdb ${SIM}/questa/fcov_ucdb/rv64gc_WALLY*.ucdb -logfile ${SIM}/questa/fcov_logs/log vcover merge -out ${SIM}/questa/fcov_ucdb/fcov.ucdb ${SIM}/questa/fcov_ucdb/rv64gc_I_WALLY-COV-add.elf.ucdb ${SIM}/questa/fcov_ucdb/rv64gc_I_WALLY*.ucdb -logfile ${SIM}/questa/fcov_logs/log
vcover report -details -html ${SIM}/questa/fcov_ucdb/fcov.ucdb vcover report -details -html ${SIM}/questa/fcov_ucdb/fcov.ucdb
vcover report ${SIM}/questa/fcov_ucdb/fcov.ucdb -details -cvg > ${SIM}/questa/fcov/fcov.log vcover report ${SIM}/questa/fcov_ucdb/fcov.ucdb -details -cvg > ${SIM}/questa/fcov/fcov.log
vcover report ${SIM}/questa/fcov_ucdb/fcov.ucdb -testdetails -cvg > ${SIM}/questa/fcov/fcov.testdetails.log vcover report ${SIM}/questa/fcov_ucdb/fcov.ucdb -testdetails -cvg > ${SIM}/questa/fcov/fcov.testdetails.log

20
sim/questa/wave.do
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@ -204,7 +204,7 @@ add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/SrcAE
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/SrcBE add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/SrcBE
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/ALUResultE add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/ALUResultE
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/ResultW add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/ResultW
add wave -noupdate -expand -group {Memory Stage} /testbench/FunctionName/FunctionName add wave -noupdate -expand -group {Memory Stage} /testbench/FunctionName/FunctionName/FunctionName
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrValidM add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrValidM
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM
@ -657,22 +657,6 @@ add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/WFITimeoutM
add wave -noupdate -expand -group testbench /testbench/DCacheFlushStart add wave -noupdate -expand -group testbench /testbench/DCacheFlushStart
add wave -noupdate /testbench/dut/core/lsu/hptw/hptw/HPTWLoadPageFault add wave -noupdate /testbench/dut/core/lsu/hptw/hptw/HPTWLoadPageFault
add wave -noupdate /testbench/dut/core/lsu/hptw/hptw/HPTWLoadPageFaultDelay add wave -noupdate /testbench/dut/core/lsu/hptw/hptw/HPTWLoadPageFaultDelay
add wave -noupdate -expand -group rvvi /testbench/rvvi_synth/rvvisynth/clk
add wave -noupdate -expand -group rvvi /testbench/rvvi_synth/rvvisynth/rvvi
add wave -noupdate -expand -group rvvi /testbench/rvvi_synth/rvvisynth/valid
add wave -noupdate -group packetizer -color Gold /testbench/rvvi_synth/packetizer/CurrState
add wave -noupdate -group packetizer -radix unsigned /testbench/rvvi_synth/packetizer/WordCount
add wave -noupdate -group packetizer /testbench/rvvi_synth/packetizer/RVVIStall
add wave -noupdate -group packetizer /testbench/rvvi_synth/packetizer/rvviDelay
add wave -noupdate -group packetizer -expand -group axi-write-interface /testbench/rvvi_synth/packetizer/RvviAxiWdata
add wave -noupdate -group packetizer -expand -group axi-write-interface /testbench/rvvi_synth/packetizer/RvviAxiWlast
add wave -noupdate -group packetizer -expand -group axi-write-interface /testbench/rvvi_synth/packetizer/RvviAxiWstrb
add wave -noupdate -group packetizer -expand -group axi-write-interface /testbench/rvvi_synth/packetizer/RvviAxiWvalid
add wave -noupdate -group packetizer -expand -group axi-write-interface /testbench/rvvi_synth/packetizer/RvviAxiWready
add wave -noupdate -expand -group eth /testbench/rvvi_synth/ethernet/mii_tx_clk
add wave -noupdate -expand -group eth /testbench/rvvi_synth/ethernet/mii_txd
add wave -noupdate -expand -group eth /testbench/rvvi_synth/ethernet/mii_tx_en
add wave -noupdate -expand -group eth /testbench/rvvi_synth/ethernet/mii_tx_er
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 4} {640 ns} 1} {{Cursor 4} {2400 ns} 1} {{Cursor 3} {554 ns} 0} {{Cursor 4} {120089 ns} 0} WaveRestoreCursors {{Cursor 4} {640 ns} 1} {{Cursor 4} {2400 ns} 1} {{Cursor 3} {554 ns} 0} {{Cursor 4} {120089 ns} 0}
quietly wave cursor active 4 quietly wave cursor active 4
@ -690,4 +674,4 @@ configure wave -griddelta 40
configure wave -timeline 0 configure wave -timeline 0
configure wave -timelineunits ns configure wave -timelineunits ns
update update
WaveRestoreZoom {0 ns} {1033211 ns} WaveRestoreZoom {0 ns} {755549 ns}

2
src/cache/cache.sv vendored
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// cache.sv // cache.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Rose Thompson ross1728@gmail.com
// Created: 7 July 2021 // Created: 7 July 2021
// Modified: 20 January 2023 // Modified: 20 January 2023
// //

2
src/cache/cachefsm.sv vendored
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// cachefsm.sv // cachefsm.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Rose Thompson ross1728@gmail.com
// Created: 25 August 2021 // Created: 25 August 2021
// Modified: 20 January 2023 // Modified: 20 January 2023
// //

2
src/cache/subcachelineread.sv vendored
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// subcachelineread.sv // subcachelineread.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Rose Thompson ross1728@gmail.com
// Created: 4 February 2022 // Created: 4 February 2022
// Modified: 20 January 2023 // Modified: 20 January 2023
// //

2
src/ebu/ahbcacheinterface.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// ahbcacheinterface.sv // ahbcacheinterface.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Rose Thompson ross1728@gmail.com
// Created: August 29, 2022 // Created: August 29, 2022
// Modified: 18 January 2023 // Modified: 18 January 2023
// //

2
src/ebu/ahbinterface.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// ahbinterface.sv // ahbinterface.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Rose Thompson ross1728@gmail.com
// Created: August 29, 2022 // Created: August 29, 2022
// Modified: 18 January 2023 // Modified: 18 January 2023
// //

2
src/ebu/buscachefsm.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// busfsm.sv // busfsm.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Rose Thompson ross1728@gmail.com
// Created: December 29, 2021 // Created: December 29, 2021
// Modified: 18 January 2023 // Modified: 18 January 2023
// //

2
src/ebu/busfsm.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// busfsm.sv // busfsm.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Rose Thompson ross1728@gmail.com
// Created: December 29, 2021 // Created: December 29, 2021
// Modified: 18 January 2023 // Modified: 18 January 2023
// //

2
src/ebu/controllerinput.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// controllerinput.sv // controllerinput.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Rose Thompson ross1728@gmail.com
// Created: August 31, 2022 // Created: August 31, 2022
// Modified: 18 January 2023 // Modified: 18 January 2023
// //

2
src/ebu/ebu.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// abhmulticontroller // abhmulticontroller
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Rose Thompson ross1728@gmail.com
// Created: August 29, 2022 // Created: August 29, 2022
// Modified: 18 January 2023 // Modified: 18 January 2023
// //

2
src/ebu/ebufsmarb.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// ebufsmarb.sv // ebufsmarb.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Rose Thompson ross1728@gmail.com
// Created: 23 January 2023 // Created: 23 January 2023
// Modified: 23 January 2023 // Modified: 23 January 2023
// //

2
src/generic/arrs.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// arrs.sv // arrs.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Rose Thompson ross1728@gmail.com
// Modified: November 12, 2021 // Modified: November 12, 2021
// //
// Purpose: resets are typically asynchronous but need to be synchronized to // Purpose: resets are typically asynchronous but need to be synchronized to

2
src/ifu/bpred/RASPredictor.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// RASPredictor.sv // RASPredictor.sv
// //
// Written: Ross Thomposn ross1728@gmail.com // Written: Rose Thomposn ross1728@gmail.com
// Created: 15 February 2021 // Created: 15 February 2021
// Modified: 25 January 2023 // Modified: 25 January 2023
// //

2
src/ifu/bpred/bpred.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// bpred.sv // bpred.sv
// //
// Written: Ross Thomposn ross1728@gmail.com // Written: Rose Thomposn ross1728@gmail.com
// Created: 12 February 2021 // Created: 12 February 2021
// Modified: 19 January 2023 // Modified: 19 January 2023
// //

2
src/ifu/bpred/btb.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// btb.sv // btb.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Rose Thompson ross1728@gmail.com
// Created: February 15, 2021 // Created: February 15, 2021
// Modified: 24 January 2023 // Modified: 24 January 2023
// //

2
src/ifu/bpred/gshare.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// gshare.sv // gshare.sv
// //
// Written: Ross Thompson // Written: Rose Thompson
// Email: ross1728@gmail.com // Email: ross1728@gmail.com
// Created: 16 March 2021 // Created: 16 March 2021
// Adapted from ssanghai@hmc.edu (Shreya Sanghai) // Adapted from ssanghai@hmc.edu (Shreya Sanghai)

2
src/ifu/bpred/gsharebasic.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// gsharebasic.sv // gsharebasic.sv
// //
// Written: Ross Thompson // Written: Rose Thompson
// Email: ross1728@gmail.com // Email: ross1728@gmail.com
// Created: 16 March 2021 // Created: 16 March 2021
// Adapted from ssanghai@hmc.edu (Shreya Sanghai) global history predictor implementation. // Adapted from ssanghai@hmc.edu (Shreya Sanghai) global history predictor implementation.

2
src/ifu/bpred/icpred.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// icpred.sv // icpred.sv
// //
// Written: Ross Thomposn ross1728@gmail.com // Written: Rose Thomposn ross1728@gmail.com
// Created: February 26, 2023 // Created: February 26, 2023
// Modified: February 26, 2023 // Modified: February 26, 2023
// //

2
src/ifu/bpred/localaheadbp.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// localaheadbp // localaheadbp
// //
// Written: Ross Thompson // Written: Rose Thompson
// Email: ross1728@gmail.com // Email: ross1728@gmail.com
// Created: 16 March 2021 // Created: 16 March 2021
// //

2
src/ifu/bpred/localbpbasic.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// localbpbasic // localbpbasic
// //
// Written: Ross Thompson // Written: Rose Thompson
// Email: ross1728@gmail.com // Email: ross1728@gmail.com
// Created: 16 March 2021 // Created: 16 March 2021
// //

2
src/ifu/bpred/localrepairbp.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// localrepairbp // localrepairbp
// //
// Written: Ross Thompson // Written: Rose Thompson
// Email: ross1728@gmail.com // Email: ross1728@gmail.com
// Created: 15 April 2023 // Created: 15 April 2023
// //

2
src/ifu/bpred/satCounter2.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// satCounter2.sv // satCounter2.sv
// //
// Written: Ross Thomposn // Written: Rose Thomposn
// Email: ross1728@gmail.com // Email: ross1728@gmail.com
// Created: February 13, 2021 // Created: February 13, 2021
// Modified: // Modified:

2
src/ifu/bpred/twoBitPredictor.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// twoBitPredictor.sv // twoBitPredictor.sv
// //
// Written: Ross Thomposn // Written: Rose Thomposn
// Email: ross1728@gmail.com // Email: ross1728@gmail.com
// Created: February 14, 2021 // Created: February 14, 2021
// Modified: // Modified:

2
src/ifu/irom.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// irom.sv // irom.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Rose Thompson ross1728@gmail.com
// Created: 30 January 2022 // Created: 30 January 2022
// Modified: 18 January 2023 // Modified: 18 January 2023
// //

2
src/ifu/spill.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// spill.sv // spill.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Rose Thompson ross1728@gmail.com
// Created: 28 January 2022 // Created: 28 January 2022
// Modified: 19 January 2023 // Modified: 19 January 2023
// //

2
src/lsu/atomic.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// atomic.sv // atomic.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Rose Thompson ross1728@gmail.com
// Created: 31 January 2022 // Created: 31 January 2022
// Modified: 18 January 2023 // Modified: 18 January 2023
// //

2
src/lsu/dtim.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// dtim.sv // dtim.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Rose Thompson ross1728@gmail.com
// Created: 30 January 2022 // Created: 30 January 2022
// Modified: 18 January 2023 // Modified: 18 January 2023
// //

2
testbench/common/DCacheFlushFSM.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// DCacheFlushFSM.sv // DCacheFlushFSM.sv
// //
// Written: David Harris David_Harris@hmc.edu and Ross Thompson ross1728@gmail.com // Written: David Harris David_Harris@hmc.edu and Rose Thompson ross1728@gmail.com
// Modified: 14 June 2023 // Modified: 14 June 2023
// //
// Purpose: The L1 data cache and any feature L2 or high cache will not necessary writeback all dirty // Purpose: The L1 data cache and any feature L2 or high cache will not necessary writeback all dirty

2
testbench/common/functionName.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// functionName.sv // functionName.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Rose Thompson ross1728@gmail.com
// //
// Purpose: decode name of function // Purpose: decode name of function
// //

6
testbench/common/loggers.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// loggers.sv // loggers.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Rose Thompson ross1728@gmail.com
// Modified: 14 June 2023 // Modified: 14 June 2023
// //
// Purpose: Log branch instructions, log instruction fetches, // Purpose: Log branch instructions, log instruction fetches,
@ -246,8 +246,8 @@ module loggers import cvw::*; #(parameter cvw_t P,
flop #(1) ResetDReg(clk, reset, resetD); flop #(1) ResetDReg(clk, reset, resetD);
assign resetEdge = ~reset & resetD; assign resetEdge = ~reset & resetD;
initial begin initial begin
LogFile = "branch.log"; // will break some of Ross's research analysis scripts LogFile = "branch.log"; // will break some of Rose's research analysis scripts
CFILogFile = "cfi.log"; // will break some of Ross's research analysis scripts CFILogFile = "cfi.log"; // will break some of Rose's research analysis scripts
//LogFile = $psprintf("branch_%s%0d.log", P.BPRED_TYPE, P.BPRED_SIZE); //LogFile = $psprintf("branch_%s%0d.log", P.BPRED_TYPE, P.BPRED_SIZE);
file = $fopen(LogFile, "w"); file = $fopen(LogFile, "w");
CFIfile = $fopen(CFILogFile, "w"); CFIfile = $fopen(CFILogFile, "w");

2
testbench/common/watchdog.sv
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// watchdog.sv // watchdog.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Rose Thompson ross1728@gmail.com
// Modified: 14 June 2023 // Modified: 14 June 2023
// //
// Purpose: Detects if the processor is stuck and halts the simulation // Purpose: Detects if the processor is stuck and halts the simulation

2
testbench/sdc/sdModel.sv
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@ -917,7 +917,7 @@ module sdModel
WRITE_DATA: begin WRITE_DATA: begin
oeDat<=1; oeDat<=1;
outdly_cnt<=outdly_cnt+1; outdly_cnt<=outdly_cnt+1;
datOut <= 4'b1111; // listen... until I tell you otherwise, DAT bus is all high (thanks Ross) datOut <= 4'b1111; // listen... until I tell you otherwise, DAT bus is all high (thanks Rose)
if ( outdly_cnt > `DLY_TO_OUTP) begin // if (outdly_cnt > 47) NAC cycles elapsed if ( outdly_cnt > `DLY_TO_OUTP) begin // if (outdly_cnt > 47) NAC cycles elapsed

2
tests/custom/fpga-test-sdc/copyFlash.c
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// copyFlash.sv // copyFlash.sv
// //
// Written: Ross Thompson September 25, 2021 // Written: Rose Thompson September 25, 2021
// Modified: // Modified:
// //
// Purpose: copies flash card into memory // Purpose: copies flash card into memory

2
tests/custom/fpga-test-sdc/sdcDriver.c
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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// SDC.sv // SDC.sv
// //
// Written: Ross Thompson September 25, 2021 // Written: Rose Thompson September 25, 2021
// Modified: // Modified:
// //
// Purpose: driver for sdc reader. // Purpose: driver for sdc reader.

2
tests/custom/simple/fail.s
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@ -1,4 +1,4 @@
# Ross Thompson # Rose Thompson
# March 17, 2021 # March 17, 2021
# Oklahoma State University # Oklahoma State University