From fe9b6129b83e5b437cad5d516a5f54d7b651ce86 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 6 Apr 2024 16:17:42 -0700 Subject: [PATCH 1/6] Starting to add more testfloat --- bin/regression-wally | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index 0cd195db7..4155d0d1e 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -298,7 +298,20 @@ else: # testfloat tests if (testfloat): configs = [] - testfloatconfigs = [ + + testfloatconfigs = ["fdqh_ieee_rv64gc", "fdq_ieee_rv64gc", "fdh_ieee_rv64gc", "fd_ieee_rv64gc", "fh_ieee_rv64gc", "f_ieee_rv64gc", "fdqh_ieee_rv32gc", "f_ieee_rv32gc"] + for config in testfloatconfigs: + tests = ["div", "sqrt", "add", "sub", "mul", "cvtint", "cvtfp", "fma", "cmp"] + for test in tests: + tc = TestCase( + name=test, + variant=config, + cmd="wsim --tb testbench_fp --sim questa " + config + " " + test, + grepstr="All Tests completed with 0 errors") + configs.append(tc) + + + testfloatdivconfigs = [ "fdh_ieee_div_2_1_rv32gc", "fdh_ieee_div_2_1_rv64gc", "fdh_ieee_div_2_2_rv32gc", "fdh_ieee_div_2_2_rv64gc", "fdh_ieee_div_2_4_rv32gc", "fdh_ieee_div_2_4_rv64gc", "fdh_ieee_div_4_1_rv32gc", "fdh_ieee_div_4_1_rv64gc", "fdh_ieee_div_4_2_rv32gc", @@ -324,7 +337,7 @@ if (testfloat): "f_ieee_div_4_1_rv32gc", "f_ieee_div_4_1_rv64gc", "f_ieee_div_4_2_rv32gc", "f_ieee_div_4_2_rv64gc", "f_ieee_div_4_4_rv32gc", "f_ieee_div_4_4_rv64gc" ] - for config in testfloatconfigs: + for config in testfloatdivconfigs: # div test case tests = ["div", "sqrt"] if ("ieee" in config): From fec160d6f901dda5ed1b250a862540d601067f39 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 6 Apr 2024 21:38:44 -0700 Subject: [PATCH 2/6] Updated coremark to use wsim --- addins/riscv-arch-test | 2 +- benchmarks/coremark/Makefile | 3 ++- benchmarks/coremark/coremark_sweep.py | 1 + bin/regression-wally | 2 +- 4 files changed, 5 insertions(+), 3 deletions(-) diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index 8a52b016d..8a0cdceca 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit 8a52b016dbe1e2733cc168b9d6e5c93e39059d4d +Subproject commit 8a0cdceca9f0b91b81905eb8497f6586bf8d1c6b diff --git a/benchmarks/coremark/Makefile b/benchmarks/coremark/Makefile index a73dc6eea..9ac905950 100644 --- a/benchmarks/coremark/Makefile +++ b/benchmarks/coremark/Makefile @@ -28,7 +28,8 @@ PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \ all: $(work_dir)/coremark.bare.riscv.elf.memfile run: - (cd ../../sim && (time vsim -c -do "do wally-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log)) + time wsim rv$(XLEN)gc coremark 2>&1 | tee $(work_dir)/coremark.sim.log + #(cd ../../sim && (time vsim -c -do "do wally-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log)) $(work_dir)/coremark.bare.riscv.elf.memfile: $(work_dir)/coremark.bare.riscv riscv64-unknown-elf-objdump -D $< > $<.elf.objdump diff --git a/benchmarks/coremark/coremark_sweep.py b/benchmarks/coremark/coremark_sweep.py index 82a596604..045121a46 100755 --- a/benchmarks/coremark/coremark_sweep.py +++ b/benchmarks/coremark/coremark_sweep.py @@ -73,6 +73,7 @@ with open('coremark_results.csv', mode='w', newline='') as csvfile: os.system(make_all) make_run = f"make run XLEN={xlen_value} ARCH={arch}" + print("Running: " + make_run) output = os.popen(make_run).read() # Capture the output of the command # Extract the Coremark values using regular expressions diff --git a/bin/regression-wally b/bin/regression-wally index 4236afc9a..c161a9340 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -306,7 +306,7 @@ if (testfloat): tc = TestCase( name=test, variant=config, - cmd="wsim --tb testbench_fp --sim questa " + config + " " + test, + cmd="wsim --tb testbench_fp " + config + " " + test, grepstr="All Tests completed with 0 errors") configs.append(tc) From 0b3bb722806f1613607b0a5488293bc38643196d Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 6 Apr 2024 21:48:06 -0700 Subject: [PATCH 3/6] Added missing fdh_ieee_rv64gc derived config --- config/derivlist.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/config/derivlist.txt b/config/derivlist.txt index 1c4f19fe2..3f6a869d9 100644 --- a/config/derivlist.txt +++ b/config/derivlist.txt @@ -587,6 +587,9 @@ IEEE754 1 deriv fd_ieee_rv64gc fd_rv64gc IEEE754 1 +deriv fdh_ieee_rv64gc fdh_rv64gc +IEEE754 1 + deriv fdq_ieee_rv64gc fdq_rv64gc IEEE754 1 From d182a2925eacc689e7129cdab7d7fa7aa1e24479 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 7 Apr 2024 05:40:18 -0700 Subject: [PATCH 4/6] Fixed bug in testbench_fp for XLEN > FLEN --- testbench/testbench_fp.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/testbench/testbench_fp.sv b/testbench/testbench_fp.sv index ed58a9992..ba35a3c14 100644 --- a/testbench/testbench_fp.sv +++ b/testbench/testbench_fp.sv @@ -821,8 +821,8 @@ module testbench_fp; case (UnitVal) `FMAUNIT: Res = FpRes; `DIVUNIT: Res = FpRes; - `CMPUNIT: Res = {{(FLEN-XLEN){1'b0}}, CmpRes}; - `CVTINTUNIT: if (WriteIntVal) Res = {{(FLEN-XLEN){1'b0}}, IntRes}; else Res = FpRes; + `CMPUNIT: Res = {{(FLEN > XLEN ? FLEN-XLEN : XLEN-FLEN){1'b0}}, CmpRes}; + `CVTINTUNIT: if (WriteIntVal) Res = {{(FLEN > XLEN ? FLEN-XLEN : XLEN-FLEN){1'b0}}, IntRes}; else Res = FpRes; `CVTFPUNIT: Res = FpRes; endcase From 60e70c1986b8df2da2f1b5e538fd0cbc60590dc4 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 8 Apr 2024 05:57:18 -0700 Subject: [PATCH 5/6] Fixed testbench-fp replication length for regression-wally --testfloat. Changed regression-wally to expect -- in named arguments. --- bin/regression-wally | 28 ++++++++++++++++------------ testbench/testbench_fp.sv | 6 +++--- 2 files changed, 19 insertions(+), 15 deletions(-) diff --git a/bin/regression-wally b/bin/regression-wally index c161a9340..bdb58fea0 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -254,20 +254,20 @@ os.chdir(regressionDir) coveragesim = "questa" # Questa is required for code/functional coverage defaultsim = "questa" # Default simulator for all other tests; change to Verilator when flow is ready -coverage = '-coverage' in sys.argv -fp = '-fp' in sys.argv -nightly = '-nightly' in sys.argv -testfloat = '-testfloat' in sys.argv +coverage = '--coverage' in sys.argv +fp = '--fp' in sys.argv +nightly = '--nightly' in sys.argv +testfloat = '--testfloat' in sys.argv if (nightly): - nightMode = "-nightly"; + nightMode = "--nightly"; sims = ["questa", "verilator", "vcs"] else: nightMode = ""; sims = [defaultsim] if (coverage): # only run RV64GC tests in coverage mode - coverStr = '-coverage' + coverStr = '--coverage' else: coverStr = '' @@ -302,6 +302,8 @@ if (testfloat): testfloatconfigs = ["fdqh_ieee_rv64gc", "fdq_ieee_rv64gc", "fdh_ieee_rv64gc", "fd_ieee_rv64gc", "fh_ieee_rv64gc", "f_ieee_rv64gc", "fdqh_ieee_rv32gc", "f_ieee_rv32gc"] for config in testfloatconfigs: tests = ["div", "sqrt", "add", "sub", "mul", "cvtint", "cvtfp", "fma", "cmp"] + if ("f_" in config): + tests.remove("cvtfp") for test in tests: tc = TestCase( name=test, @@ -343,6 +345,8 @@ if (testfloat): if ("ieee" in config): tests.append("cvtint") tests.append("cvtfp") + if ("f_" in config): + tests.remove("cvtfp") for test in tests: tc = TestCase( name=test, @@ -362,26 +366,26 @@ def main(): except: pass - if '-makeTests' in sys.argv: + if '--makeTests' in sys.argv: os.chdir(regressionDir) os.system('./make-tests.sh | tee ./logs/make-tests.log') - if '-all' in sys.argv: + if '--all' in sys.argv: TIMEOUT_DUR = 30*7200 # seconds #configs.append(getBuildrootTC(boot=True)) - elif '-buildroot' in sys.argv: + elif '--buildroot' in sys.argv: TIMEOUT_DUR = 30*7200 # seconds #configs=[getBuildrootTC(boot=True)] - elif '-coverage' in sys.argv: + elif '--coverage' in sys.argv: TIMEOUT_DUR = 20*60 # seconds # Presently don't run buildroot because it has a different config and can't be merged with the rv64gc coverage. # Also it is slow to run. # configs.append(getBuildrootTC(boot=False)) os.system('rm -f cov/*.ucdb') - elif '-nightly' in sys.argv: + elif '--nightly' in sys.argv: TIMEOUT_DUR = 60*1440 # 1 day #configs.append(getBuildrootTC(boot=False)) - elif '-testfloat' in sys.argv: + elif '--testfloat' in sys.argv: TIMEOUT_DUR = 60*60 # seconds else: TIMEOUT_DUR = 10*60 # seconds diff --git a/testbench/testbench_fp.sv b/testbench/testbench_fp.sv index ba35a3c14..f124ec334 100644 --- a/testbench/testbench_fp.sv +++ b/testbench/testbench_fp.sv @@ -1275,7 +1275,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( 2'b01: begin // quad -> long X = {TestVector[8+P.XLEN+P.Q_LEN-1:8+(P.XLEN)]}; SrcA = {P.XLEN{1'bx}}; - Ans = {{(P.FLEN-64){1'b0}}, TestVector[8+(P.XLEN-1):8]}; + Ans = {{(P.FLEN > 64 ? P.FLEN-64 : 0){1'b0}}, TestVector[8+(P.XLEN-1):8]}; end 2'b00: begin // quad -> int X = {TestVector[8+32+P.Q_LEN-1:8+(32)]}; @@ -1327,7 +1327,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( 2'b01: begin // single -> long X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.XLEN+P.S_LEN-1:8+(P.XLEN)]}; SrcA = {P.XLEN{1'bx}}; - Ans = {{(P.FLEN-64){1'b0}}, TestVector[8+(P.XLEN-1):8]}; + Ans = {{(P.FLEN > 64 ? P.FLEN-64 : 0){1'b0}}, TestVector[8+(P.XLEN-1):8]}; end 2'b00: begin // single -> int X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+32+P.S_LEN-1:8+(32)]}; @@ -1353,7 +1353,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) ( 2'b01: begin // half -> long X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.XLEN+P.H_LEN-1:8+(P.XLEN)]}; SrcA = {P.XLEN{1'bx}}; - Ans = {{(P.FLEN-64){1'b0}}, TestVector[8+(P.XLEN-1):8]}; + Ans = {{(P.FLEN > 64 ? P.FLEN-64 : 0){1'b0}}, TestVector[8+(P.XLEN-1):8]}; end 2'b00: begin // half -> int X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+32+P.H_LEN-1:8+(32)]}; From f5602d8b55f8c89b88ffd8dadc508b4efbebae56 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 8 Apr 2024 05:57:50 -0700 Subject: [PATCH 6/6] Ignore coremark_results --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index 963128c60..528de54dc 100644 --- a/.gitignore +++ b/.gitignore @@ -190,3 +190,4 @@ sim/verilator/logs sim/verilator/wkdir sim/vcs/logs sim/vcs/wkdir +benchmarks/coremark/coremark_results.csv