diff --git a/testbench/testbench.sv b/testbench/testbench.sv
index b0255262f..fb12eb082 100644
--- a/testbench/testbench.sv
+++ b/testbench/testbench.sv
@@ -335,6 +335,10 @@ module testbench;
         $display("Benchmark: coremark is done.");
         $stop;
       end
+    if (P.ZICSR_SUPPORTED & dut.core.ifu.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.ieu.InstrValidM) begin 
+      $display("Program fetched illegal instruction 0x00000000 from address 0x00000000.  Might be fault with no fault handler.");
+      //$stop; // presently wally32/64priv tests trigger this for reasons not yet understood.
+    end
     if(Validate) begin
       if (TEST == "embench") begin
         // Writes contents of begin_signature to .sim.output file
diff --git a/testbench/tests.vh b/testbench/tests.vh
index d1d7ddda6..573f5c20b 100644
--- a/testbench/tests.vh
+++ b/testbench/tests.vh
@@ -1425,10 +1425,10 @@ string imperas32f[] = '{
     "rv64i_m/Zfh/src/fcvt.wu.h_b27-01.S",
     "rv64i_m/Zfh/src/fcvt.wu.h_b28-01.S",
     "rv64i_m/Zfh/src/fcvt.wu.h_b29-01.S",
-    "rv64i_m/Zfh/src/fcvt.h.l_b25-01.S",
-    "rv64i_m/Zfh/src/fcvt.h.l_b26-01.S",
-    "rv64i_m/Zfh/src/fcvt.h.lu_b25-01.S",
-    "rv64i_m/Zfh/src/fcvt.h.lu_b26-01.S",
+//    "rv64i_m/Zfh/src/fcvt.h.l_b25-01.S", // tests commented out because they involve a fsd that hangs on vsim -c -do "do wally-batch.do fh_rv64gc arch64zfh" which lacks fsd support
+//    "rv64i_m/Zfh/src/fcvt.h.l_b26-01.S",
+//    "rv64i_m/Zfh/src/fcvt.h.lu_b25-01.S",
+//    "rv64i_m/Zfh/src/fcvt.h.lu_b26-01.S",
     "rv64i_m/Zfh/src/fcvt.l.h_b1-01.S",
     "rv64i_m/Zfh/src/fcvt.l.h_b22-01.S",
     "rv64i_m/Zfh/src/fcvt.l.h_b23-01.S",