Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

On the way to making vcu108 work again.

Browse Source
This commit is contained in:
Rose Thompson 2024-08-23 14:45:22 -07:00
parent 4d56b3ca96
commit b471913d9f
2 changed files with 259 additions and 920 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

139
fpga/constraints/constraints-ArtyA7.xdc
View File

@ -7,8 +7,8 @@
create_generated_clock -name SPISDCClock -source [get_pins clk_out3_xlnx_mmcm] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncore.uncore/sdc.sdc/SPICLK]
##### clock #####
set_property PACKAGE_PIN E3 [get_ports {default_100mhz_clk}]
set_property IOSTANDARD LVCMOS33 [get_ports {default_100mhz_clk}]
set_property PACKAGE_PIN E3 [get_ports default_100mhz_clk]
set_property IOSTANDARD LVCMOS33 [get_ports default_100mhz_clk]
##### RVVI Ethernet ####
# taken from https://github.com/alexforencich/verilog-ethernet/blob/master/example/Arty/fpga/fpga.xdc
@ -34,7 +34,7 @@ create_clock -period 40.000 -name phy_rx_clk [get_ports phy_rx_clk]
create_clock -period 40.000 -name phy_tx_clk [get_ports phy_tx_clk]
set_false_path -to [get_ports {phy_ref_clk phy_reset_n}]
set_output_delay 0 [get_ports {phy_ref_clk phy_reset_n}]
set_output_delay 0.000 [get_ports {phy_ref_clk phy_reset_n}]
##### GPI ####
set_property PACKAGE_PIN A8 [get_ports {GPI[0]}]
@ -87,16 +87,16 @@ set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.000 [ge
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 2.000 [get_ports resetn]
set_max_delay -from [get_ports resetn] 20.000
set_false_path -from [get_ports resetn]
set_property PACKAGE_PIN C2 [get_ports {resetn}]
set_property IOSTANDARD LVCMOS33 [get_ports {resetn}]
set_property PACKAGE_PIN C2 [get_ports resetn]
set_property IOSTANDARD LVCMOS33 [get_ports resetn]
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.000 [get_ports south_reset]
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 2.000 [get_ports south_reset]
set_max_delay -from [get_ports south_reset] 20.000
set_false_path -from [get_ports south_reset]
set_property PACKAGE_PIN D9 [get_ports {south_reset}]
set_property IOSTANDARD LVCMOS33 [get_ports {south_reset}]
set_property PACKAGE_PIN D9 [get_ports south_reset]
set_property IOSTANDARD LVCMOS33 [get_ports south_reset]
@ -125,15 +125,27 @@ set_property IOSTANDARD LVCMOS33 [get_ports {south_reset}]
#set_property PULLUP true [get_ports {SDCCD}]
# SDCDat[3]
set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCS}]
set_property PACKAGE_PIN D4 [get_ports SDCCS]
set_property IOSTANDARD LVCMOS33 [get_ports SDCCS]
set_property PULLTYPE PULLUP [get_ports SDCCS]
# set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[2]}]
# set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[1]}]
# SDCDat[0]
set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCIn}]
set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCLK}]
set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCmd}]
set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCD}]
set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCWP}]
set_property PACKAGE_PIN F4 [get_ports SDCIn]
set_property IOSTANDARD LVCMOS33 [get_ports SDCIn]
set_property PULLTYPE PULLUP [get_ports SDCIn]
set_property PACKAGE_PIN F3 [get_ports SDCCLK]
set_property IOSTANDARD LVCMOS33 [get_ports SDCCLK]
set_property PULLTYPE PULLUP [get_ports SDCCLK]
set_property PACKAGE_PIN D3 [get_ports SDCCmd]
set_property IOSTANDARD LVCMOS33 [get_ports SDCCmd]
set_property PULLTYPE PULLUP [get_ports SDCCmd]
set_property PACKAGE_PIN H2 [get_ports SDCCD]
set_property IOSTANDARD LVCMOS33 [get_ports SDCCD]
set_property PULLTYPE PULLUP [get_ports SDCCD]
set_property PACKAGE_PIN G2 [get_ports SDCWP]
set_property IOSTANDARD LVCMOS33 [get_ports SDCWP]
set_property PULLTYPE PULLUP [get_ports SDCWP]
set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCCS}]
@ -158,54 +170,54 @@ set_max_delay -datapath_only -from [get_pins xlnx_ddr3_c0/u_xlnx_ddr3_mig/u_memc
# ddr3
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[0]]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[1]]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[2]]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[3]]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[4]]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[5]]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[6]]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[7]]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[8]]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[9]]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[10]]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[11]]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[12]]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[13]]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[14]]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[15]]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dm[0]]
set_property IOSTANDARD SSTL135 [get_ports ddr3_dm[1]]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[0]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[1]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[2]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[3]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[4]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[5]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[6]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[7]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[8]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[9]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[10]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[11]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[12]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[13]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[14]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[15]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dm[0]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_dm[1]}]
set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[0]]
set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[0]]
set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[1]]
set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[1]]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[13]]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[12]]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[11]]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[10]]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[9]]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[8]]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[7]]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[6]]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[5]]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[4]]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[3]]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[2]]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[1]]
set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[0]]
set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[2]]
set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[1]]
set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[0]]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[13]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[12]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[11]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[10]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[9]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[8]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[7]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[6]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[5]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[4]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[3]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[2]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[1]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[0]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[2]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[1]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[0]}]
set_property IOSTANDARD DIFF [get_ports ddr3_ck_p[0]]
set_property IOSTANDARD DIFF [get_ports ddr3_ck_n[0]]
set_property IOSTANDARD SSTL135 [get_ports ddr3_ras_n]
set_property IOSTANDARD SSTL135 [get_ports ddr3_cas_n]
set_property IOSTANDARD SSTL135 [get_ports ddr3_we_n]
set_property IOSTANDARD SSTL135 [get_ports ddr3_reset_n]
set_property IOSTANDARD SSTL135 [get_ports ddr3_cke[0]]
set_property IOSTANDARD SSTL135 [get_ports ddr3_odt[0]]
set_property IOSTANDARD SSTL135 [get_ports ddr3_cs_n[0]]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_cke[0]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_odt[0]}]
set_property IOSTANDARD SSTL135 [get_ports {ddr3_cs_n[0]}]
set_properity PACKAGE_PIN K5 [get_ports ddr3_dq[0]]
@ -257,3 +269,28 @@ set_properity PACKAGE_PIN N5 [get_ports ddr3_cke[0]]
set_properity PACKAGE_PIN R5 [get_ports ddr3_odt[0]]
set_properity PACKAGE_PIN U8 [get_ports ddr3_cs_n[0]]
create_clock -period 40.000 -name VIRTUAL_clk_out3_mmcm -waveform {0.000 20.000}
set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports {GPI[*]}]
set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports {GPI[*]}]
set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports SDCCD]
set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCCD]
set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports SDCIn]
set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCIn]
set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports SDCWP]
set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCWP]
set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports UARTSin]
set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports UARTSin]
create_clock -period 12.000 -name VIRTUAL_clk_pll_i -waveform {0.000 6.000}
set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports {GPO[*]}]
set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports {GPO[*]}]
set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports SDCCLK]
set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 0.000 [get_ports SDCCLK]
set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports SDCCS]
set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCCS]
set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports SDCCmd]
set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCCmd]
set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports UARTSout]
set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports UARTSout]
#set_output_delay -clock [get_clocks VIRTUAL_clk_pll_i] -min -add_delay 0.000 [get_ports ddr3_reset_n]
#set_output_delay -clock [get_clocks VIRTUAL_clk_pll_i] -max -add_delay 80.000 [get_ports ddr3_reset_n]

1002
fpga/src/fpgaTop.sv
View File

File diff suppressed because it is too large Load Diff