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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

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This commit is contained in:
Ross Thompson 2022-01-27 08:45:33 -06:00
commit b44f57b6b5
6 changed files with 6 additions and 1766 deletions
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0
pipelined/config/rv32emc/BTBPredictor.txt → pipelined/config/rv32etim/BTBPredictor.txt
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0
pipelined/config/rv32emc/twoBitPredictor.txt → pipelined/config/rv32etim/twoBitPredictor.txt
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8
pipelined/config/rv32emc/wally-config.vh → pipelined/config/rv32etim/wally-config.vh
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@ -50,9 +50,9 @@
`define UARCH_PIPELINED 1 `define UARCH_PIPELINED 1
`define UARCH_SUPERSCALR 0 `define UARCH_SUPERSCALR 0
`define UARCH_SINGLECYCLE 0 `define UARCH_SINGLECYCLE 0
`define MEM_DTIM 0 `define MEM_DTIM 1
`define MEM_DCACHE 0 `define MEM_DCACHE 0
`define MEM_IROM 0 `define MEM_IROM 1
`define MEM_ICACHE 0 `define MEM_ICACHE 0
`define MEM_VIRTMEM 0 `define MEM_VIRTMEM 0
`define VECTORED_INTERRUPTS_SUPPORTED 1 `define VECTORED_INTERRUPTS_SUPPORTED 1
@ -73,7 +73,7 @@
// Integer Divider Configuration // Integer Divider Configuration
// DIV_BITSPERCYCLE must be 1, 2, or 4 // DIV_BITSPERCYCLE must be 1, 2, or 4
`define DIV_BITSPERCYCLE 4 `define DIV_BITSPERCYCLE 1
// Legal number of PMP entries are 0, 16, or 64 // Legal number of PMP entries are 0, 16, or 64
`define PMP_ENTRIES 0 `define PMP_ENTRIES 0
@ -89,7 +89,7 @@
`define BOOTROM_RANGE 34'h00000FFF `define BOOTROM_RANGE 34'h00000FFF
`define RAM_SUPPORTED 1'b1 `define RAM_SUPPORTED 1'b1
`define RAM_BASE 34'h80000000 `define RAM_BASE 34'h80000000
`define RAM_RANGE 34'h07FFFFFF `define RAM_RANGE 34'h0000FFFF
`define EXT_MEM_SUPPORTED 1'b0 `define EXT_MEM_SUPPORTED 1'b0
`define EXT_MEM_BASE 34'h80000000 `define EXT_MEM_BASE 34'h80000000
`define EXT_MEM_RANGE 34'h07FFFFFF `define EXT_MEM_RANGE 34'h07FFFFFF

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setup.sh
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@ -23,6 +23,8 @@ export PATH=/usr/local/bin/verilator:$PATH # Change this for your path to Verila
# ModelSim/Questa (vsim) # ModelSim/Questa (vsim)
export PATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin:$PATH # Change this for your path to Modelsim export PATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin:$PATH # Change this for your path to Modelsim
export MGLS_LICENSE_FILE=1717@solidworks.eng.hmc.edu # Change this to your Siemens license server export MGLS_LICENSE_FILE=1717@solidworks.eng.hmc.edu # Change this to your Siemens license server
export PATH=/cad/synopsys/SYN/bin:$PATH # Change this for your path to Design Compiler
# *** license
# Imperas; *** remove if not using; *** fix paths # Imperas; *** remove if not using; *** fix paths
export PATH=$RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64:$PATH # *** maybe take this out based on Imperas export PATH=$RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64:$PATH # *** maybe take this out based on Imperas

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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/references/PIPELINE.reference_output
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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/PIPELINE.S
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