diff --git a/wally-pipelined/src/cache/ICacheCntrl.sv b/wally-pipelined/src/cache/ICacheCntrl.sv
index 629ec7cc5..35851defd 100644
--- a/wally-pipelined/src/cache/ICacheCntrl.sv
+++ b/wally-pipelined/src/cache/ICacheCntrl.sv
@@ -141,7 +141,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256)
   logic 		       FetchCountFlag;
   localparam FetchCountThreshold = WORDSPERLINE - 1;
   
-  logic [LOGWPL:0] 	       FetchCount, NextFetchCount;
+  logic [LOGWPL-1:0] 	       FetchCount, NextFetchCount;
 
   logic [`PA_BITS-1:0] 	       PCPreFinalF, PCPSpillF;
   logic [`PA_BITS-1:OFFSETWIDTH] PCPTrunkF;
@@ -195,10 +195,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256)
 
   assign spill = PCPF[4:1] == 4'b1111 ? 1'b1 : 1'b0;
   assign hit = ICacheMemReadValid; // note ICacheMemReadValid is hit.
-  // verilator lint_off WIDTH
-  // *** Bug width is wrong.
-  assign FetchCountFlag = (FetchCount == FetchCountThreshold);
-  // verilator lint_on WIDTH
+  assign FetchCountFlag = (FetchCount == FetchCountThreshold[LOGWPL-1:0]);
   
   // Next state logic
   always_comb begin
@@ -404,7 +401,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256)
   // to compute the fetch address we need to add the bit shifted
   // counter output to the address.
 
-  flopenr #(LOGWPL+1) 
+  flopenr #(LOGWPL) 
   FetchCountReg(.clk(clk),
 		.reset(reset | CntReset),
 		.en(CntEn),
diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv
index 61102b468..82343b864 100644
--- a/wally-pipelined/src/cache/dcache.sv
+++ b/wally-pipelined/src/cache/dcache.sv
@@ -108,7 +108,7 @@ module dcache
   logic [`XLEN-1:0]	       ReadDataWordM, ReadDataWordMuxM;
   logic [`XLEN-1:0]	       FinalWriteDataM, FinalAMOWriteDataM;
   logic [BLOCKLEN-1:0]	       FinalWriteDataWordsM;
-  logic [LOGWPL:0] 	       FetchCount, NextFetchCount;
+  logic [LOGWPL-1:0] 	       FetchCount, NextFetchCount;
   logic [WORDSPERLINE-1:0]     SRAMWordEnable;
   logic 		       SelMemWriteDataM;
   logic [2:0] 		       Funct3W;
@@ -319,10 +319,7 @@ module dcache
   assign ReadDataWordM = ReadDataBlockSetsM[MemPAdrM[$clog2(WORDSPERLINE+`XLEN/8) : $clog2(`XLEN/8)]];
 
 
-  // *** fix width later.
-  // verilator lint_off WIDTH
   assign HWDATA = CacheableM ? VictimReadDataBlockSetsM[FetchCount] : WriteDataM;
-  // verilator lint_on WIDTH
 
   mux2 #(`XLEN) UnCachedDataMux(.d0(ReadDataWordM),
 				.d1(DCacheMemWriteData[`XLEN-1:0]),
@@ -392,13 +389,8 @@ module dcache
   assign BasePAdrOffsetM = CacheableM ? {{OFFSETLEN}{1'b0}} : BasePAdrM[OFFSETLEN-1:0];
   assign BasePAdrMaskedM = {BasePAdrM[`PA_BITS-1:OFFSETLEN], BasePAdrOffsetM};
   
-  generate
-    if (`XLEN == 32) begin
-      assign AHBPAdr = ({{`PA_BITS-4{1'b0}}, FetchCount} << 2) + BasePAdrMaskedM;
-    end else begin
-      assign AHBPAdr = ({{`PA_BITS-3{1'b0}}, FetchCount} << 3) + BasePAdrMaskedM;
-    end
-  endgenerate
+  assign AHBPAdr = ({{`PA_BITS-LOGWPL{1'b0}}, FetchCount} << $clog2(`XLEN/8)) + BasePAdrMaskedM;
+  
     
   
   // mux between the CPU's write and the cache fetch.
@@ -422,9 +414,9 @@ module dcache
   
 
   assign AnyCPUReqM = |MemRWM | (|AtomicM);
-  assign FetchCountFlag = (FetchCount == FetchCountThreshold[LOGWPL:0]);
+  assign FetchCountFlag = (FetchCount == FetchCountThreshold[LOGWPL-1:0]);
 
-  flopenr #(LOGWPL+1) 
+  flopenr #(LOGWPL) 
   FetchCountReg(.clk(clk),
 		.reset(reset | CntReset),
 		.en(CntEn),